eispice, a clone of Berkley SPICE 3 simulation engine. It is optimised for high-speed digital design and has a front-end backed, based and powered by Python.
The design philosophy of Python lends itself to be used for simulators. By design philosophy, I mean the core philosophy that was handily jotted down in the document ‘The Zen of Python,’ which includes gems such as ‘Beautiful is better than ugly,’ ‘Simple is better than complicated’ and others like ‘Readability counts.’ Such an array of underlying principles is the reason why Python is highly extensible.
SPICE and behind the SPICE
eispice is one of those products that change the landscape of their intended use by virtue of being so good. It was initially developed and targeted towards PCB-level signal integrity simulation, simulating Input/output Buffer Information Specification (IBIS) model-defined devices, transmission lines and passive termination. Over the years though, scope of the tool has been expanded to include general-purpose simulation features as well.
Other than being the only open source simulator that provides native IBIS model support, the most unique feature of eispice is its Python based front-end. This is achieved by wrapping the simulator into a Python module that makes it possible to use Python language to control simulations and process results. If you are not strong with Python, but do work on Berkley SPICE, you can use Python shell instead of nutmeg, and Python scripts can be run like batch-mode SPICE.