In this article we take a closer look at the three EDA solutions offered by Dolphin Integration: hierarchical schematic editor, SLED; mixed-signal simulator, SMASH; and its extension for power consumption analysis, SCROOGE
Dolphin Integration is a company based in Grenoble, France. The company produces electronic design automation (EDA) software, MEMS converters, regulators, silicon intellectual property (IP) of audio codecs, memories, and also provides custom fabless services.
Let’s take a closer look at three of its EDA tools, their functions and the advantages they offer to design engineers.
SLED schematic editor
SLED is a hierarchical schematic entry solution by Dolphin Integration that allows designers to perform graphic entry and configuration of their designs in much less time. It efficiently blends the feasibility of linking components along with interactively and graphically configuring design contexts for hierarchical netlisting. It also improves designers’ productivity by enabling the creation of true mixed-signal circuits, multi-level and multi-domain systems.
Key benefits. SLED provides a user-friendly interface. It allows file exchange with other schematic entry tools along with other tools in the design chain. It also supports the most common modelling languages such as SPICE, Verilog, Verilog-A, VHDL and VHDL-AMS, and enables modelling of micro electromechanical systems (MEMS) and multi-domain systems, thanks to the features supporting graphic VHDL link editing. SLED delivers a dynamic link with mixed-signal simulator SMASH (discussed later) for schematic-driven design.
SLED allows creation of multiple levels of descriptions for system or single-block validation, while also combining SPICE and HDL representations to ease the architectural design of any system-on-chip (SoC). A system can be iteratively validated by using a SPICE representation of a single block, while all other blocks in the system are represented in HDL for a fully-functional mixed-signal simulation. It is fundamental for state-of-the-art hierarchical designs of multi-domain components. For design of analogue circuits, the generic library of SPICE components combined with multi-flavour SPICE netlisting improves designers’ productivity by enabling creation of true mixed-signal circuits.
Ease of use. SLED has a direct syntax colourised behavioural code display to facilitate reading of HDL and HDL-AMS models. It comes with easy push/pop navigation through a list of hierarchical schematics. It has click-‘n’-drop symbols of any blocks from any generic or ad-hoc library and drags them while preserving wire connections.
Schematic consistency checks. SLED saves time due to early error detection during design with coherency checks, i.e., symbol vs model I/O, and online electrical rule checks, i.e., shorted output pins.
Interoperability and compatibility. The design data—including design or reference library configuration files, symbols, schematics—is stored in an ASCII format, enabling a script-based approach for automatic symbol generation, library conversion and design library setup. It comes with a built-in handling of design context configurations for multi-flavour SPICE netlisting (SMASH, Hspice, SDL, LVS).
EDIF import/export. The option to import/export to and from EDIF provides the means to exchange full schematics including graphics with other design entry solutions, as well as to transfer designs to the next step in your design chain, such as schematic-driven layout.
Design of multi-domain systems. SLED offers the capability to create highly flexible and complex models through graphic composition. It covers the modelling of any domain like analogue electronics, digital electronics, mechanics, magnetic and thermal effects. SLED is ideal for multi-domain systems where designers are guided with intelligent-type checking of terminals during wiring of symbols. Initialising homogeneous simulation of such heterogenic systems in SMASH avoids simulator couplings with its disadvantages in configuration, setup and convergence problems.
SCROOGE power consumption estimator
SCROOGE is a power consumption analyser for simulating mixed-signal power consumption hierarchically. Where the common solutions just enable statistical or average power consumption analysis, the USP of SCROOGE is in providing a hierarchical evaluation of power consumption.
SCROOGE is the ideal solution for companies wondering on how to take a step towards efficient power estimations. Its capability to provide results for a complete mixed-signal design enables precise power optimisations and sizing of the components.
Key benefits. It is functionally very easy to integrate SCROOGE in your flow as it is easy to reduce power consumption all along the design chain through accurate transient analysis of the peaks on your SoC. You can easily optimise the sequencing of an SoC by identifying the most consuming parts, without any need for any other data. SCROOGE lets you avoid design iterations with your P&R provider with a clock tree emulation available after synthesis.
SCROOGE TLA grants logic, analogue and mixed-signal design engineers with the capability to quantify power consumption, to track and locate all power peaks. As the logic part of a design is only one face of the coin, analogue designers share the need to address other issues in time domain, beginning with the resilience of switching margins. SCROOGE TLA is an EDA solution that provides the capability to analyse hierarchically the mixed-signal sensitivity to power consumption, which is a key feature for yield optimisation of logic.
Interactive analysis. SCROOGE allows concurrent simulation of mixed-signal transient analysis and power consumption along with display of analogue, leakage and dynamic power consumption as well as intrinsic capacitances for each power supply during transient simulation. It helps in the identification of critical points with current peaks in correlation with intrinsic capacitances.
How it helps in reducing power consumption. The software lets you avoid design oversizing, resulting in improved density and speed. It detects circuit defaults and predicts power consumption much earlier in the flow, thus saving designers’ time by providing them with an easy, efficient and usable solution.
Reducing the peaks of a dynamic mixed-signal power consumption simulation grants the consistent benefit of smoothing-out the disturbances threatening high-resolution analogue parts, including sensitive read-margins of logic parts.
Power analysis is best performed in the time domain, while noise resilience is best analysed over the spectral domain. SCROOGE is an add-on to all the ASIC options supporting logic structural and behavioural languages, empowering the true mixed-signal simulator with capabilities to simulate dynamic power consumption and leakage. Back-annotation of SPEF parasitic capacitances provides the ability to check with high accuracy the model for consumption after layout.
SMASH mixed-signal simulator
As the silicon geometries shrink year by year, device models are becoming more and more complex and the number of elements that must be included in any simulation are invariably on the rise. Today, a simulator must not only accommodate such advances but also provide features and options to allow effective circuit development to be completed.
SMASH is a mixed-signal, multi-language, multi-level, single-kernel simulator. Thus it allows device definition in primitive devices or high-level descriptions, handles analogue and discrete-level signals, and recognises a range of net-list languages from SPICE and other high-level description languages. In addition, it allows net-lists to include a variety of the different languages it recognises (electrical, structural, functional and behavioural) while allowing synchronisation of analogue and digital partitions without delay, instability or distortion. The end result is a fast, accurate mixed-signal simulator.
With mixed-signal simulator SMASH, designers benefit from innovative features that enable efficient and fast detection of design defects with a fine control for tuning the speed accuracy trade-offs. These features help designers improve their design productivity for a faster and safer time-to-fab.
Key benefits. SMASH has a state-of-the-art single kernel for easy mixing of multi-language, mixed-signal and multi-domain descriptions. It supports most of the modelling languages like SPICE, Verilog, VHDL, Verilog-A(MS) and VHDL-AMS. It also allows automatic insertion of configurable interface devices as needed between logic and analogue parts.
SMASH has simultaneous display of analogue and logic simulation results in an interactive waveform viewer during the analysis runtime and in post-processing. It has an easy setup of trade-off between speed and accuracy plus added-value features for design bug detection and eradication. The simulator has multi-threading capabilities that help in reducing simulation runtime along with a swift algorithm to accelerate the time-domain electrical simulations of transistor-based circuits.
Intuitive simulation setup. SMASH houses a powerful mixed-signal and multi-language netlisting setup in SLED with dynamic link for cross-probing. It has a user-friendly and intuitive graphic interface for the setup of simulation patterns. The software has features to enable the direct re-use of simulation setup for power consumption analysis with SCROOGE.
How it helps in fast bug detection. The software has in-built dynamic electrical rule checker to automatically detect electrical rule violations for any device, model, net or expression during the simulation. It contains multiple operating point analyses to identify improper operating states that can cause characterisation failures, requiring a design iteration and at worst field failures. SMASH has features enabling import and export of audio files to listen to the output of various applications going from the audio form to physical devices before the prototyping stage. All these features invariably assist in faster bug detection.
The author is a tech correspondent at EFY Bengaluru