Kactus2: An Easy-to-Use Design Tool for Embedded Systems


Kactus2 is a graphical open source IP-XACT toolset that will make the design process of embedded systems easier even for a novice engineer. It is growing into an open reference for benchmarking other metadata-based tools

Anagha P.

Kactus2 is metadata-based software for sketching, packing, integrating and generating both hardware and software for embedded products at several hierarchy levels. It is the first graphical open source design environment that is IEEE1685/IP-XACT compatible, and is used to design embedded multiprocessor system-on-chip (MPSoC) products. It enables easier reuse of IP and practical hardware/software abstraction for smooth development of application software, thereby increasing productivity. This software is created by assembling application-specific components on general-purpose platforms, and the components are packetised to a metadata library. The use of metadata ensures less error-prone design.

Fig. 1: Configure library

Developed by Tampere University of Technology (Finland) for its Funbase project, Kactus2 gives an easy start to metadata-based designs even without prior expertise. It makes field programmable gate arrays (FPGAs) easy for software engineers and provides hardware abstraction for programmers with the use of multicore communication application programming interfaces (MCAPIs). Kactus2 comes with an intuitive user interface. It is also equipped with built-in generators for top VHDL, Modelsim and Altera Quartus projects. Kactus2 is mostly written in C++ and has a young but well-established codebase.

Who will benefit from Kactus2?
Kactus2 is ideal for small- and mid-sized vendors and integrators who currently have only the conventional software like Office (Doc, Excel, PowerPoint, etc) for specifications/documentation and VHDL, C/C++ and FPGA tools for designs. It helps easily start a metadata-based design, increasing the manageability of the product while still using the conventional tools mentioned earlier.

Fig. 2: Creating a new bus

The software is useful for universities and research laboratories that implement new content (IP blocks, software modules, etc). Kactus2 helps packetise the content in a standard way, thus enabling the use and reuse of data by others, particularly when the original contributor leaves, for instance, after a PhD project.

Kactus2 offers a great R&D environment for bigger companies and tool providers that already have modern design tool flows and resources for developing higher abstraction methods. It offers a platform for trying new methodologies and user interface innovations.

Kactus2 helps the user create quick drafts of block diagram blueprints for printed circuit board (PCB), integrated chip (IC), SoC and IP, and store the files in the IP-XACT format. It can draft Multicore Association’s MCAPI endpoints and channel designs for all processors and fixed IPs in a product. It also generates code templates (VHDL entities and headers) for new IP blocks from descriptions of IP-XACT components.

This software creates electronic datasheets of your existing IPs, which are stored in the library as templates and blocks, ready for integration. It imports and integrity-checks IP libraries from any standard compatible IP vendor and exports your IP library. These features facilitate the reuse and exchange of IPs.

Kactus2 aids in the creation of hardware designs with hierarchy, software architecture in MCAPI communication abstraction and system designs that map software to hardware. It configures all designs, i.e., it sets the requirements, constraints, optimisation, active views, etc. This tool generates structural top-level VHDL and performs software builds for all processors. It also creates combined documentation from all blocks, through all hierarchy levels.

Fig. 3: Creating a new HW component

However, Kactus2 cannot create IP functionality. HDL editors and integrated development environment (IDE) software should be used for that. TCE tools may also be used to create C-to-VHDL so that IP can be created from C source without knowing any HDL. Another drawback is that it doesn’t allow the generation of binary and executable files either. Additional HDL synthesis and software compilation tools should be used for this purpose.

System requirements
Operating system: Linux, Windows 7, Windows Vista or Windows XP.

The installation is simple and takes only minutes. Download the *.exe file that your OS supports. Double clicking on it opens the installation window. Go through the procedure to install Kactus2 on your computer.

Configure library paths
Clicking on the Configure library icon from the Library in the top pane opens a dialogue box. Browse and add the location where you downloaded the library from opencores.org to make sure that you can access the files created from different computers. This should be set every time Kactus2 is accessed from a different computer.

Create a bus
The bus is pre-given in the exercise library.

To create a new bus, go to File, select New, and in the new window that appears, select Bus from the left hand menu. On the right side will be several VLNV fields, as shown in Fig. 2.

According to the IP-XACT format, each object should be given a unique identifier defined by the fields’ vendor, library, name and version. In this example, we are using the naming
convention specified in Set Vendor to ‘Altera.’ Use ‘ip.hwp.communication’ for the Library field, ‘avalon_bus’ for the Name field, and ‘1.0’ for the Version field. Click OK to create the new bus.

Normally, after creating the bus, we define the bus signals in the appeared ‘avalon (1.0) [bus]’ tab. But this example focuses on creating hierarchical system and documentation features of Kactus2. So now we can create buses without any signals; hence, close that tab.

Creating a hardware component
This is similar to creating a new bus. Go to File→New. Select HW Component from the left hand menu of the pop-up window. The Product Hierarchy option lets you choose which type of component you are specifying; select IP from the pull down menu. The Firmness option gives information on how the component can be modified; select Template from this pull-down menu.

Fill in the VNVL fields with your G (group 3 would use G03, etc…), ‘ip.hwp.cpu,’ ‘nios2,’ and ‘1.0’ as given in Fig. 3. Create the ‘hardware component’ by pressing OK.

After creating the component, a new tab opens which is filled with information about the component. In the given example, the only bits of information to be filled for each component are the bus interfaces and CPU details.

Fig. 4: Adding interfaces to components

Adding interfaces to components
We only need ‘avalon_bus’ for the Nios2 processor component. From the list shown on the Nios2 tab, select Bus Interfaces. Double click on the empty list space to create a new bus interface and type ‘Avalon_Master’ in the name field. You can also give a display name and description to this interface.

It is to be noted that you are not able to edit the Bus Definition column in the Bus Interfaces list. Open the bus interface by going to the tree view: Bus Interfaces→Avalon Master and double click on it. In order to tie the bus interface to the actual bus, we should fill in the Bus definition and Abstraction definition fields. This is done by using the drag and drop method from the hierarchy pane. Expand ‘avalon_bus’ from the hierarchy pane to show the Abstraction definition for this bus. The resulting bus interface definition would look like what’s shown in Fig. 4.

Fig. 5: Address space addition

The next thing to specify is the interfacing mode for the bus interface. The most typical setting is either master or slave mode, and can be found from the Interface mode section. Here the Nios2 processor acts as master on the ‘avalon_bus.’ so select Master from the pull-down menu shown in ‘Error! Reference source not found.’ You can add more bus interfaces to it using the same basic principle.

We can identify the created component as a CPU component by adding address space to it. Select Address spaces from the list given on the left. Add a new address space to the address space summary list, and fill the cells as shown in Fig. 5. Now the component can be identified as a programmable one. Select CPUs, double click the empty area to add a new line to the list, give a name to it, select the address space reference to the created ‘avalon_addr_space’ and save the component.

Creating channel components
This component is pre-given in the exercise work library.

To make HIBI bus, we need to make a special component that represents the HIBI interconnection network. Create normal components with product hierarchy IP, and fill the VLNV fields as G, ‘ip.hwp.communication,’ ’hibi,’ and ‘draft.’ The following bus interfaces need to be added to the component:

1. Slave interface to system_clk_bus

2. Slave interface to rst_n_bus

3. Mirrored master interface to hibi_bus

4. Second mirrored master interface to hibi_bus

5. Third mirrored master interface to hibi_bus

On creating the required bus interfaces, select Channels from the list on the Nios2 tab, and press the ‘+’ button to create a new channel. Enter ‘hibi_Channel’ in the Name field. Double click on the Bus interference reference field and select all hibi_bus bus interfaces to be added to the channel. Now the window will look like what’s shown in Fig. 6.

Fig. 6: Creating channel components

Creating a hierarchical design
When all components and buses are made, we can proceed to the actual hierarchical system design. Go to File→New, select HW design from the pop-up, select SoC from the Product Hierarchy and Mutable from the Firmness pull-down menu. Fill in the VNLV tuple and click on OK to create a new hardware design.

Fig. 7: Creating hierarchical design

Drag and drop different components to the design using the Hierarchy or VLNV Tree menu on the left. Tools are provided in the Diagram Tools in the top pane for creating ports and connecting components together with buses.

Some of the basics of Kactus2 have been covered here. By successfully completing the exercise work systems with Kactus2, you can use available IP-XACT components, create your own components, or use draft components.

Download now: click here

The author is a tech correspondent at EFY Bengaluru


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