Are you working on a new electronics project from scratch? Does it include a designing-and-automating process? Do you have all the required electronics design and automation (EDA) tools for the same? I understand that such projects need a lot of designing tools, and it is tough to find all EDA tools separately and then install these one by one on Windows. So, if you are well-versed with Fedora operating system (OS) and are using one, the solution to all your problems would be Fedora Electronic Laboratory (FEL).
FEL is a spin on Fedora that contains all software one would require for EDA. It provides all the different open source hardware design flows depending on the semiconductor industry’s current trends.
Reason for existence
The usual problem that designers have at hand is that they do not find any open source EDA solution for a real-life problem. Now, while engineers use EDA software to design chips or circuit boards, it requires a set of hardware design tools to design chips. However, the same set of hardware design tools need not work with every hardware design project. Although FEL is limited to Fedora OS, it could make its existence possible only because it had the solution to all problems discussed above.
The open source EDA software included in FEL meets the demands of field-proven problems. This open source platform helps you keep in pace with the current technological race with open source community support. This community helps users with installation and use of any EDA tool in the spin.
FEL as a platform has the ability to map the three methodologies—design, simulation and verification. These methodologies enable one to have a better hardware design flow and experience. These also help Fedora achieve its aim to support innovation and development brought by the open source community.
Collaborative hardware review
The digital hardware design has many requirements, one of which is to track files and feed these into multiple EDA tools. Then, reports and netlists have to be analysed carefully and logged-in further. All of these are tracked by the companies under project dependent files. Fedora makes all of these processes easy through a dedicated web server, meant especially for hardware design and code reviews through FEL. It also helps improve their sign-off methodologies.
Designers are often confused about hardware code reviews, and inexperienced companies are often misguided due to which plenty of time is wasted. Moreover, code-sharing takes place in an inefficient way (in a non-acceptable format) due to which misunderstandings arise. This web server solves all these issues, collaborating all hardware tools and their files.
Targets micro-nano electronic engineering field
FEL targets the engineering field at the micro and nano level with the help of its different tools. On one hand, the collection of Perl modules included provide the engineering support at Verilog or very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) level, while on the other hand, there are tools for embedded design that provide advanced RISC machines (ARM) support as an alternative to Fedora architecture. The extra standard cell libraries included support more than 300MB of cells of size 0.13µm.
Then, there are C based design methodologies, programmable logic array (PLA) tools and simulators for 8051 and 8085 microcontrollers along with the peer-review solution, coupled with Elipse-integrated development environment (IDE) to support the intellectual property (IP) design for digital or embedded hardware, extracted spice decks (sub-circuits with external connectors that appear in an alphabetical order) with simulation facility through gnucap, ngspice or any other spice simulator.
Features that dominate
FEL’s methodologies make it a multi-purpose platform, where at one time it allows design and simulation, while at the other synthesises the design flow.
Design and simulation. The application-specific integrated circuit (ASIC) analogue design-and-simulation tool helps designers to edit their schematics and to simulate them. This category includes both general-purpose drawing programs and specific computer aided design (CAD) tools, like XCircuit and various simulators from general-purpose to mixed-level (for example, gnucap, ngspice or gspiceui). When design tools allow one to generate publishable quality of circuit diagrams, simulators perform all types of circuit analysis at a level beyond the capabilities of Spice implementations. These tools are multi-lingual, can mimic different variants of Spice and can also support new languages, such as Verilog-AMS.
Design rule checks (DRC). FEL platform allows layouts for ASICs using tools like Magic, Electric, Toped and Netgen. These also help in generating database formats, like GDSII stream and crystallographic information file (CIF), from a given layout to enable easy file transfer based on industry standards. During operation, a continuous DRC operates in the background and provides an updated report of the violations in the design, if any. After the design is complete, a hierarchical circuit extractor re-extracts the part of the circuit that has been changed and permits an interactive stretching and compaction, routing the tools to work under and around existing connections.
Successful compilation and verification. FEL provides a hardware description language (HDL) simulation environment that allows you to verify functional timing models of the designs. It contains tools like GHDL, quite universal circuit simulator (Qucs), FreeHDL, Icarus Verilog, GTKWave and Drawtiming to scale-up the multiple levels of complexities and abstractions in the design. These support both VHDL and Verilog designs and allow cross-reference generation in HTML. Standard cell libraries help generate automatic layouts from VHDL description, which is then successfully compiled and run on DLX and LEON1 SPARC processor.
Logical design flow. Tools like pharosc, Alliance and gds2pov are more such design tools in FEL that not only route and automate the layout generation but also layout the design flow. These provide a complete real-time logic (RTL) for CIF and GDSII formats and create a three-dimensional view of the scenes described in GDSII files. Complete checking of the model and format proofing occurs at this stage.
Students working on Fedora have liked FEL a lot from the time it was just a project. They not only want to contribute towards it as users but also as developers.
A student at http://blog.gmane.org/ says that she has been working on Fedora electronic spin since quite some time now. She has liked working with this so much that she has also worked as an ambassador promoting the advantages of FEL. She herself started using Fedora only with FEL and admires this platform so much that she wants other students to get an opportunity to learn and use it.
Another student in the same blog says that he has heard about FEL, admires it and wants to contribute towards it, being a part of this project.
Even though it has many positive features, you will find designers who are not sure if they want to use FEL, because they have never used Fedora and are not sure if they will be able to partition their existing OS to allocate space for Fedora. But, I think that every new tool has certain challenges in the beginning that can be sorted out further with extended usage, especially when there is free-of-cost community support where you only need to share your problems and the solutions come to you.
A single platform with so many design-and-simulation tools to learn and use, FEL has plenty of advantages for the electronics design and simulation industry. Make sure to try your hands at it.
The author is a technical journalist at EFY