Since hardware designs are now being churned out in large numbers, it has become challenging for designers to increase the adoption rate and at the same time keep pace with new developments. But thanks to the software tools which are maturing at par with the hardware developments and helping the design engineers to overcome these challenges.
If we see the latest developments, Silicon Valley is getting equipped with a new generation of design tools which are easy to adopt, scalable to design, economical to build and help reduce time-to-market the new innovations. Almost all silicon vendors have taken up more integrated approach in terms of coming up with their own development environment and support.
On software side, emphasis has been on performance analysis and better utilisation of CPU cores, while hardware developments are getting assisted better with the help of more and more simplified and integrated IDE approaches.
From simple PCB designing to complex FPGA and embedded board designs, we have a variety of software tools available with rich sets of features to help design easy, simplified and optimised designs. Let us see how these tools have matured in recent times.
Performance analysis support
On software front, if we look at the new features, focus has been particularly on performance analysis. There have been various enhancements and developments in software for better utilisation of CPU cores and system memory, improving overall efficiency of the embedded design tools.
For instance, TI’s code composer studio has been enhanced immensely to help analyse performance of DSP as well as CPU cores. Mentor Graphics also announced next-generation Sourcery CodeBench and Sourcery Analyzer products to allow developers accelerate system debugging, including concurrent Linux applications, by quick and easy visualisation and analysis of complex software systems.
Also, the latest version of Intel System Studio includes an all-new analyser which analyses system and SOC events. The new GUI displays the hardware events with call stacks, and results can be seen in source or assembly without any instrumentation.
Virtual JTAG probes
Software applications can be tested against IDEs and the hardware can be developed for dedicated logics simulated on the design tools, and you can easily get all the bugs out. But when the entire system is put together, interacting with the processor, there occur system-level problems which are very hard to capture.
Arun Mulpur, industry marketing manager, MathWorks, says, “The most basic question while talking about hardware/software co-design/debug is, where do I start? Whether to start with hardware and then write software, or first software then hardware? But actually doing both at the same time in the same environment is the solution. Simulink embraces this approach as a system-level simulation and implementation platform for both hardware and software.”
The latest embedded design suites are addressing these system-level problems with new capabilities where software breakpoints can trigger hardware data capture and vice-versa. You can execute instruction traces or have your hardware breakpoints to halt application debugs to easily find out system-level problems, saving time and costs.
Mentor’s Embedded Sourcery Codebench Virtual Environment for software debug and Veloce Emulator allow hardware-software co-debug. You can use Veloche GUI to download hardware design and Sourcery Codebench Virtual Environment for software development and then debug through a virtual JTAG probe connected to the processor.
Embedded design suite from Xilinx also comes with the software/hardware cross feature, enabling software and hardware teams to debug in the same environment and allowing each team to capture both software and hardware data without having to use or learn separate tools.
Reduced bring-up time
For software validation in context of system hardware, methodologies like prototyping are widely used, and FPGA-based prototyping has surfaced with the solutions. But there are certain associated challenges.
The bring-up time to implement a design into an FPGA prototype has become a major challenge these days. It is not easy to make changes to the register-transfer level (RTL) design. Also, there hasn’t been an easy transition available from an existing simulation or emulation environment to the prototype.
Same bring-up flow for emulation and rapid prototyping enables designers to switch seamlessly between two execution engines, which in-turn reduces the prototype bring-up time significantly as compared to traditional FPGA-based prototyping approaches.
The Protium platform from Cadence, based on Xilinx Virtex-7 2000T FPGAs and featuring an advanced implementation and debug software flow, addresses the above challenges. Common compile flow between Palladium emulation and Protium FPGA-based prototyping allow designers to have a quick and efficient transition from emulation to prototyping.
The platform supports up to 100 million gates, which is a 4X increase in capacity compared to the first-generation Rapid Prototyping Platform. A fully automatic software flow enables fast prototype bring-up while additional user-driven performance optimisations assure highest possible speed, which is essential for early software development.
power aware feature
This feature can be seen as a part of new performance analysis features that were mentioned earlier. In-depth analysis of performance and events of CPU and GPU activities allow identification of wake-up causes, timers triggered for different applications and various interrupts. Now you can maximise power efficiency of the silicon using functions provided in software tools.
Precision 32 from Silicon Labs enables developers to maximise power efficiency of embedded 32-bit designs. It features a power estimation view where the relative power profile of any given configuration can be seen and analysed. You can then make optimisations to the configuration using the tool and improve overall power consumption of the system.
Increasing hardware and software complexity in SoC designs has made low-power designing even more challenging. Juergen Jaeger, senior manager, product management and marketing, Cadence Design Systems, Inc., explains, “The low-power requirements in many SoC devices (like mobile) exponentially increases hardware and software complexity in terms of clocking, power regions, etc, which in return requires cycle-accurate, yet high-performance tools to validate the system functionality.”
Intel System Studio has come up with an all-new power profiler, Intel Energy Feature, which can analyse CPU core frequencies and events that wake up the processor at source code level. It also includes two support watches for Android systems: SoC Watch and WakeUp Watch. While SoC Watch monitors power states, frequencies and wake-up metrics that provide insight into the system’s energy efficiency, WakeUp Watch traces and monitors system power states from the command line.
Dynamic Power Analysis in the Palladium XP II platform from Cadence is now integrated with verification and debug support for the IEEE 1801 standard for design and verification of low-power integrated circuits. With this, the Cadence System Development Suite now offers an integrated and consistent low-power flow for engineers using either of the power standards across the simulation and verification platforms, with common power plan and metrics, and integrated debug analysis.
These features will enable the designers to address low-power requirements in SoC designs and further reduce time-to-market for the products, while at the same time improving product quality.
The Internet of Things (IoT) is the next-generation field which almost everyone is talking about these days. Latest versions of almost all the development tools, including TI’s Code Composer, Simplicity Studio from Silicon Labs, Design Suits from Xilinx and many others include support for the latest processors focusing on IoT developments and designs.
But apart from these applications, an all-new SQL Planner has been introduced to ease data analysis and management for intelligent devices. SQL Planner from ITTIA is included in its database engine which calculates critical data statistics efficiently with cost-based optimisations. It provides a smart query optimiser that determines the most efficient way to execute a given query by considering plausible query plans, thus accelerating SQL query execution and reducing the time to access data.
SQL Planner can be an important embedded data management tool to help devices gain intelligence in machine-to-machine (M2M) frameworks and thus IoT ecosystems. These devices are enabled to analyse data and determine when objects must be replaced, repaired or recalled.
Automatic NEON vectorisation
NEON is a single instruction multiple data (SIMD) architecture extension implemented as part of ARM processor. But it has its own execution pipelines and a distinct register bank. If you are working with applications based on ARM Cortex-A processors, especially with multimedia and signal processing applications, the support for NEON vectorisation becomes crucial.
IAR embedded workbench has introduced the possibility to automatically vectorise code, enabling you to achieve faster application response time, improved application battery lifetime and the other requirements of low cost and low power.
Low-cost target hardware platforms like Arduino, Raspberry Pi and others have become popular among designers as well as education community. This popularity has forced the design tools to have support for these interesting designing blocks. This new feature will not only help the designer community but the education sector as well.
Simulink, which offers block diagram environment for model-based design and simulation, now includes support for prototyping, testing and running models on such low-cost target hardware as Arduino, Lego Mindstorms NXT and Raspberry Pi in its latest version. The latest version also supports Samsung Galaxy Android devices.
For real-time applications
Also, Simulink product family now has a new member, Simulink Real-Time. It allows you to create real-time applications from different models and run them on dedicated as well as custom target computer hardware connected to your physical system.
With the existing support for real-time simulation and testing, rapid control prototyping, DSP and vision system prototyping, and hardware-in-the-loop (HIL) simulations, you can extend your Simulink models with driver blocks, automatically generate real-time applications, define instrumentation, and perform interactive or automated runs on a dedicated target computer equipped with a real-time kernel, multicore CPU, I/O and protocol interfaces, and FPGAs.
With growing demand for compact and efficient systems, it is getting difficult to have everything fitted inside a box and at the same time maintain reasonable cost. The size constraint can be met with the help of rigid-flex PCB technology, though most tools do not include folding and fitting aspects of rigid-flex designs.
To eliminate these constrains and reduce manual work needed for designing rigid-flex PCBs, the latest version of Altium Designer is equipped with support for flex and rigid-flex designs, including schematic capture, 3D PCB layout, analysis and programmable design—all in a single unified platform. This allows smaller packaging of electronic designs, leading to lower cost of materials and production, and increased durability as well.
A single-layer-stack PCB tool cannot support rigid-flex designs, as both rigid and flex sections may use different sets of layers. The new enhanced layer stack management system supports the definition and naming of multiple stacks to support this design requirement. It allows definition and naming of primary and sub-stacks on a circuit board for use in a rigid-flex circuit design.
While Altium has enhanced its layer-stack management system for supporting rigid-flex designs, OrCAD has been updated with IDX (incremental data exchange) enhancements to support flex circuit definitions. Also, you can import flex circuit bend areas from MCAD in the latest version of OrCAD.
The author wrote this as a technical journalist at EFY. He recently opted and shifted to the hands-on training division of EFY