Designing with FPGAs: Clock Management (Part 4 of 5)

Varsha Agrawal

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The focus in this article is on clock management in field-programmable gate arrays (FPGAs). It talks about the digital clock manager (DCM), which is a primitive used in FPGAs from Xilinx for dealing with all aspects of clock management. DCMs are used to implement delay-locked loop (DLL), digital frequency synthesiser, digital phase shifter (PS) and digital spread spectrum. They provide advanced clocking capabilities to multiply or divide the incoming clock frequency to synthesise a new clock frequency. They also eliminate clock skew, thereby improving system performance, and are capable of phase shifting the output clock to delay the incoming clock by a fraction of clock period. Table I lists the advanced clocking capabilities of a DCM.

What is DCM
Fig. 1 shows the functional block diagram of a DCM. As shown in the figure, it comprises four different functional units, namely, DLL, digital frequency synthesiser (DFS), PS and status logic (SL).

B44_Fig_1
Fig. 1: Functional block diagram of DCM

ACA_Table_1

Fig. 2: DCM primitive
Fig. 2: DCM primitive
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The DLL unit provides an on-chip digital deskew circuit that generates output clock signals having zero propagation delay. The input signals to the DLL unit are CLKIN and CLKFB. The output signals from the DLL are CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180 and CLKDV. The deskew circuit compensates for the delay on the routing network by monitoring the output clock (either the CLK0 or the CLK2X).

The DFS unit provides a wide and flexible range of output frequencies based on the ratio of two user-defined integers, a multiplier (CLKFX_MULTIPLY) and a divisor (CLKFX_DIVIDE). The output frequency is derived from the input clock (CLKIN) by simultaneous frequency division and multiplication.

The PS unit controls the phase relations of the DCM’s clock outputs with respect to the CLKIN input. It shifts the phase of all nine DCM clock output signals by a fixed fraction of the input clock period. The fixed phase-shift value is set at design time and loaded into the DCM during FPGA configuration.

The PS unit also provides a digital interface for the FPGA application to dynamically advance or retard the current shift value by 1/256th of the clock period. The input signals to the PS unit are PSINCDEC, PSEN and PSCLK. The output signals are PSDONE and the STATUS[0].

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B7A_Table_2

The SL unit indicates the current state of the DCM via the LOCKED and STATUS[0], STATUS[1] and STATUS[2] output signals. The LOCKED output signal indicates whether the DCM outputs are in phase with the CLKIN input or not. The STATUS output signals indicate the state of the DLL and PS operations. The RST input signal resets the DCM logic and returns it to its post-configuration state.

Fig. 2 shows the DCM primitive.

The connection ports of the DCM are described in Table II.

Using DCM
Let us see how to use the DCM wizard to configure and instantiate the DCM module.

3C3_Fig_3
Fig. 3: Project Settings window
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Fig. 4: New Source Wizard window
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Fig. 5: Adding ClockDivider.vhd in the design
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Fig. 6: Skeleton source
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Fig. 7: Select IP window
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Fig. 8: Xilinx architecture wizard-setup window
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Fig. 9: Xilinx Clocking Wizard—General Setup window

The design uses the DCM wizard to divide the input clock of 50MHz to 100kHz, which is then used to drive other circuits. One can use DCM for other applications mentioned above, including de-skewing, clock phase shifting and so on.

Steps for using the DCM wizard
1. Create an integrated software environment (ISE) project.
(i) Launch an ISE. Select Start → Programs → Xilinx ISE Design Suite 13.4_1 → ISE Design Tools → Project Navigator
(ii) In Project Navigator, select File → New Project. The new project wizard opens.
(iii) In the location option, select the folder you want to work in. (We are working in the location C:/DCM. Select C:/DCM.) Click OK.
(iv) In project name, type DCM_ClockDivider.
(v) Keep the top-level source type as HDL.
(vi) Click the Next button.
(vii) Select the family and the FPGA device type and other parameters in accordance with the FPGA and other tools you have. (We have used Virtex 5 series FPGA family, device type number XC5VLX50, package as FF676 and speed grade -1.) The project settings window looks as shown in Fig. 3.
(viii) Click Next and then Finish buttons.

C31_Fig_10
Fig. 10: Adding DCM_Divide.xaw
7CB_Fig_11
Fig. 11: Component declaration
A99_Fig_12
Fig. 12: Component instantiation

2. In the Project tab, select New Source and the New Source Wizard will appear.

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3. Select VHDL module and type ClockDivider in the File name field.

4. Check if Add to Project option is ticked. If not, tick it.

5. Click Next and I/O port of the module will be displayed in the New Source Wizard window (Fig. 4).

6. Fill the name dcm in the entity field and enter CLOCK_50MHz and RST as input ports and LOCK and CLOCK_100kHz as output ports, and click Next and then the Finish button.

7. Select ClockDivider.vhd in the sources window and then click on New Source.

8. In New Source Wizard, select IP (Core Generator and Architecture Wizard) and enter DCM_Divide in the File name field and click Next.

9. In the Hierarchy window, ClockDivider.vhd is added as shown in Fig. 5 and a new skeleton source is created with defined inputs and outputs as shown in Fig. 6.

10. The Select IP window appears on the New Source Wizard (Fig. 7). Click on View by Function. Select FPGA Features and Design → Clocking → Virtex-5. Your selection will depend on the FPGA series you are using.

11. Select Chose Wizard by Basic Function → Double Clock Frequency (DCM). Click Next and then Finish.

12. Xilinx Architecture Wizard-Setup window appears as shown in Fig. 8. Confirm that the Output File Type VHDL is selected, synthesis tool XST is selected and part number xc5vlx50-1ff676 is selected. (The part number should be the same as the part number entered by the designer earlier.)

13. Then the Xilinx Clocking Wizard—General Setup appears as shown in Fig. 9.

14. Enter 50 in the Input Clock Frequency field. Select CLKDV output and select 10 in the Divide by Value drop-down box (Fig. 9).

15. Click Next, Next and Finish to close the wizard.

16. DCM_Divide.xaw is added to the list of project source files as shown in Fig. 10. It contains the architecture wizard settings.

17. Select DCM_Divide.xaw. In the Processes tab for sources window, double click View HDL Instantiation Template. An HDL implementation file DCM_Divide.vhi opens. It comprises two items, namely, component declaration (Fig. 11) and component instantiation as shown in Fig. 12.

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18. Copy the component declaration template and paste it in the ClockDivider.vhd file in the space between ‘architecture Behavioral of dcm is’ and ‘begin’ statement as shown in Fig. 13.

19. Copy the component instantiation template and paste it in the ClockDivider.vhd file after the ‘begin’ statement as shown in Fig. 14.

20. Make the changes in the instantiation code as given below:

 

Inst_DCM_Divide : DCM_Divide PORT
MAP(

CLKIN_IN => CLOCK_50MHz,
RST_IN => RST,
CLKDV_OUT => CLOCK_100kHz,
CLKIN_IBUFG_OUT => open,
CLK0_OUT =>CLK0 ,
LOCKED_OUT => LOCK
);

The final output of ClockDivider when compiled should give a ‘…completed successfully’ message as shown in Fig. 15.

688_Fig_13
Fig. 13: Clockdivider.vhd
911_Fig_14
Fig. 14: ClockDivider with component instantiation

21. In our example, we are connecting the input clock CLOCK_50MHz directly to the DCM and taking the divided clock output CLKDV_OUT as the final output CLOCK_100kHz. After compilation, load the code into the device. The CLOCK_100kHz port generates 100kHz output, which you can verify from the oscilloscope. This signal can be used anywhere as required in the program.

FB3_Fig_15
Fig. 15: Final output

In case one needs to use the inputs and outputs of the DCM internally, they have to be declared as signals. To use CLK0_OUT clock output internally, it is portmapped to CLK0 which is declared a signal as shown below:

“signal CLK0: std_logic;”

Conclusion
This part described how to generate a clock of the desired frequency using DCMs in FPGAs. The concluding part will talk about embedded processor design using FPGAs.


Varsha Agrawal is a scientist at Laser Science and Technology Center (LASTEC), a premier DRDO lab working in the field of laser-based defence systems. She has more than 13 years of R&D experience in the design and development of a variety of systems for defence-related applications. She has authored two books and published more than 20 research papers and technical articles

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