Designing with FPGAs: I2C Master Controller (Part 1 of 5)

Varsha Agrawal

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2061

Nowadays, field programmable gate arrays (FPGAs) are widely used in a variety of embedded applications as they offer complete system solutions on a single chip including digital signal processing, data storage and processing, software-defined radio, ASIC prototyping, speech recognition, computer vision, cryptography, instrumentation, telecommunications, medical imaging, defence systems, bioinformatics, computer hardware emulation, re-configurable computing and so on. An FPGA uses an array of logic blocks, which can be configured by the user. The term ‘field programmable’ signifies that the device is programmable outside the manufacturing unit. Some of the contemporary FPGA devices offer logic complexity equivalent to that of several million system gates. Also, these devices offer features like built-in hardwired processors and related peripherals, large memory, clock management systems and support for many of the contemporary device-to-device signalling technologies.

In a nutshell, FPGAs are central to any modern electronic system design. FPGAs form a customisable chip flexible enough to be deployed in a wide range of applications. They are the backbone of many complex ‘system-on-chip’ designs.

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Fig. 1: Architecture of typical FPGA device
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Fig. 2: Start condition

Designers and application engineers are always in need of a ready reference that provides them all the critical information for their day-to-day work. This series of articles is written with an aim to help them interface FPGA with the real-world devices. This is the first part in the series, which gives a brief overview of FPGA essentials in terms of fundamental concepts and other practical information. This is followed by ready-to-use guidelines for designing I2C (inter-integrated circuit bus) master controller in an FPGA. The format of each article in the series is such that it provides the introduction to the topic, hardware connection details and VHDL code listing and description. Attempt is made to provide all details related to the topic so as to make the article a complete capsule in itself.

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Introduction to FPGA
Internal architecture of an FPGA device has three main parts, namely, array of logic blocks, programmable interconnects and I/O blocks. Fig. 1 shows the architecture of a typical FPGA. Each of the I/O blocks provides individually selectable input, output or bidirectional access to one of the general-purpose I/O pins on the FPGA package. Logic blocks in an FPGA are no more complex than a couple of logic gates or a look-up table feeding a flip-flop. Programmable interconnects not only connect logic blocks to logic blocks but also connect I/O blocks to logic blocks.

Major manufacturers of FPGA devices include Xilinx, Altera, Lattice Semiconductor, MicroSemi (Actel) and SiliconBlue Technologies. Out of these, Xilinx and Altera are the market leaders and manufacture 80 per cent of the FPGAs used in the industry. Xilinx offers Xilinx 7 series (Virtex-7, Kintex-7, Artix-7) based on the 28nm HPL process technology, Zynq-7000 family which integrates an ARM Cortex-A9 MPCore processor on 28nm FPGA, Virtex series and Spartan series of FPGAs. Altera offers the Stratix, Arria and Cyclone series of FPGAs.

Details of I²C protocol, hardware connection and VHDL code are presented in the following sections.

I²C protocol
I²C is a simple bi-directional serial bus, which supports multiple masters and slaves. The I²C protocol was developed by Philips in 1982 to reduce the connection pin count. It comprises a serial bi-directional data line (SDA) and a serial bi-directional clock line (SCL). Both these lines are open drained. SDA must be pulled up to VCC with a 5.6-kilo-ohm resistor and SCL also needs to be pulled up with the same resistor only if there are multiple masters in the system or when the slave will perform clock stretching as a flow control measure to synchronise with the master. I2C bus supports various modes, namely, the slow-speed mode (maximum speed of 10kbps), standard mode (maximum speed of 100kbps), fast mode (maximum speed of 400kbps), fast mode plus (maximum speed of 1Mbps) and high-speed mode (maximum speed of 3.4Mbps).

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528_Fig_3
Fig. 3: Data transmission
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Fig. 4: Stop condition

Each device connected to the I2C bus is software addressable by a unique address. The device that controls the sending and receiving of messages by controlling the bus access is referred to as the master and the devices that are controlled by the master are referred as slaves. Both the master and the slaves can transmit and receive messages. It is a synchronous protocol that allows a master device to initiate communication with a slave device. The master device controls the SCL, which dictates the timings of all transfers on the I2C bus.

The I²C protocol comprises a set of conditions to establish communication between the devices. These include:
1. Start condition
2. Sending of the slave address along with read/write information by the master
3. Acknowledgement by the slave device
4. Data transmission between the master and the slave device
5. Stop condition

Prior to any transmission, a start condition needs to be issued on the bus. The start condition acts as a signal to all connected ICs that something is about to be transmitted on the bus. It is initiated by the master by sending a high-to-low transition on the SDA line whilst SCL is high (Fig. 2).

After the start condition, the 7-bit slave address followed by the eighth bit is sent on the SDA line by the master, where a ‘0’ on bit indicates a write operation from the master to the slave (master is the transmitter and slave is the receiver) and a ‘1’ indicates a read operation from the slave to the master (master is the receiver and slave is the transmitter). The MSB of the address bits is sent first followed by the other bits. The value on the SDA line can be changed when SCL line is low.

The slave device whose address is the same as the address being sent out by the master responds with an acknowledgement bit on the SDA line by pulling the SDA line low during the ninth clock cycle of the SCL line. After that, the transmission takes place between the master and the slave. Each byte on the SDA line for transmission is 8 bits long with the MSB being sent first. Also, the SDA line must not be changed when SCL line is high, except for the start and the stop conditions. Any number of bytes can be transmitted, however each byte is to be followed by an acknowledgement bit. Fig. 3 shows the transmission process.

To signal the end of data transfer, the master sends a stop condition by pulling the SDA line from low to high whilst the SCL line is at high (Fig. 4).

I²C master controller implementation
In this section, the implementation of the I²C master controller using an FPGA is discussed. Any FPGA can be chosen as per the designers’ requirement. Fig. 5 shows the interconnection between the FPGA and the slave device. As one can see, there are two lines required for connecting the master and the slave devices in an I2C protocol. Multiple slave devices can be connected using the same two lines.

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Fig. 5: Master and slave connection
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Fig. 6: (a) Mealy and (b) Moore FSM

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I²C master controller in an FPGA will be implemented using a finite state machine (FSM). Any controller can be implemented using an FSM, which is a mathematical model of computation used to design both computer programs and sequential logic circuits. FSM is conceived as an abstract machine that can be used in one of a finite number of states. It can change from one state to another when initiated by a triggering event or condition referred to as transition. FSMs can be classified as Mealy FSM and Moore FSM. In a Mealy FSM, the output depends on the current input and the current state (Fig. 6 (a)) whereas in a Moore FSM, the output depends on the current state only (Fig. 6 (b)).

VHDL code listing
The VHDL code (I²C.vhd) for implementing the I2C master controller is included in this month’s EFY DVD. The slave device used here has the 7-bit address of 1001000. The designer should change the address as per the address mentioned in the datasheet of the device being used. Also, the code implements the write and the read operations for one byte of data from the slave. The designer can modify the code for writing/reading multiple bytes accordingly. The code is for single master-slave configuration.

VHDL code description
The I²C.vhd code begins with the standard library to be included. The entity section defines the interface between the I2C controller and the outside world. It includes all the input and output connections including the 50MHz clock (CLK_50MHz) and reset (Reset) as input, serial clock (SCL) as output and serial data (SDA) as input-output. SDA is an open-drain bidirectional line. therefore in the entity deceleration, SDA signal is defined as in/out so that it is capable of both input and output operations.

The architecture section defines the operations of the I²C controller and comprises two processes, namely, the Output and the Clk200kHz. The Output process implements the FSM for the I²C controller and the CLK200kHz process generates the 200kHz clock from the input clock of 50MHz. The SCL clock is derived from the 200kHz clock.

The different signals defined in the architecture section include STATE, DATA_IN and DATA_OUT which are all 8-bit standard logic vectors, CLK_200kHz which is a single-bit standard logic signal and BITCOUNT which is an integer. The constants used in the code include SLAVEADD_READ, SLAVEADD_WRITE and max200k. STATE signal defines the different states of the FSM, DATA_IN is the input data to be written to the slave by the master controller and DATA_OUT is the data read from the slave by the master controller. CLK_200kHz is the 200kHz clock from which the SCL clock is derived. SLAVEADD_READ and SLAVEADD_WRITE are 8-bit signals comprising the 7-bit slave address and the read and the write bits, respectively appended at the end.

The first statement of the architecture body is a conditional statement which sets the SDA line to either high-impedance state ‘Z’ or the logic state ‘0’ depending upon the value of SDAINT. SDA gets a ‘Z’ value if SDAINT is at logic ‘1,’ otherwise SDA gets logic ‘0’ value. This is done as the SDA is an open-drain terminal and to output logic ‘1’ on this line, we need to set this line to high-impedance state.

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Let us now understand the Output process. If RESET is in logic ‘1’ state, then the FSM is made to reset and both SCL and SDAINT are set to logic ‘1’ state and the FSM goes to the state x”00” which is the idle state. The state x”00” sets both SCL and SDAINT to high. The next state of the FSM is the state x”01” in which the start condition is executed, say, SDAINT changes from logic ‘1’ to logic ‘0’ with SCL being at logic ‘1.’ States x”02” and x”03” send the 7-bit slave address followed by the write bit. the slave address is specific to the device being addressed and is mentioned in the datasheet of the device. In our case, it is ‘1001000.’

When the value of BITCOUNT equals 8, the address bits and the write bit have been transferred and the FSM goes to state x”12” to get the acknowledgement from the slave. In case there is no acknowledgement from the slave, it goes to the state x”00” to begin the communication process again. The designer can create an error state to report the error for this situation, if desired. In case there is an acknowledgement from the slave, it goes to the state x”30”. Remember that the slave sends acknowledgement by pulling the SDA line low during the ninth clock cycle of the SCL line. States x”30” and x”31” write 8-bit data to the slave and when it is over, the FSM goes to the state x”32”. The data to be written is given in the DATA_IN signal and is specific to the application and device being used. In our case, we are writing ‘00000000’ onto the slave device.

States x”32” and x”33” check the acknowledgement signal from the slave. In case there is no acknowledgement from the slave, the FSM goes to the state x”00” and when the acknowledgement is received it goes to the state x”34”. As mentioned before, the designer can create an error state to report the error. Next, the master controller reads the data from the slave. In states x”40” and x”41”, the master controller sends the slave address followed by the read bit. States x”50” and x”51” check the acknowledgement signal from the slave. States x”52” and x”53” read the data from the slave and move it to DATA_OUT signal.

In the example mentioned here, the process of sending the address along with read and write operations has been described. The designer can write the code in accordance with the design requirements of his system.

Conclusion
This part described the fundamentals of FPGA and I2C controller implementation using an FPGA. The next part will explain how to drive an LCD using an FPGA.


Varsha Agrawal is a scientist at Laser Science and Technology Center (LASTEC), a premier DRDO lab working in the field of laser-based defence systems. She has more than 13 years of R&D experience in the design and development of a variety of systems for defence-related applications. She has authored two books and published more than 20 research papers and technical articles

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