Designing with FPGAs: Interfacing an LCD (Part 2 of 5)

Varsha Agrawal


The first part of the series discussed the implementation of I2C controller using an FPGA. The focus in this part is interfacing FPGA with LCD. The basics of LCD operation, hardware interconnection and VHDL code along with its description are presented here.

LCD operation
Liquid crystals are materials that exhibit properties of both solids and liquids. These can be classified as nematic, smectic and cholesteric. Nematic liquid crystals are generally used in LCD fabrication with the twisted nematic material being the most common. Fig. 1 shows the construction of a twisted nematic LCD display. As we can see from the figure, it comprises a cell of liquid crystal fluid, conductive electrodes, a set of polarisers and a glass casing.

Fig. 1: Construction of a twisted nematic LCD display
Fig. 2: Operation of reflective LCD display

Polarisers are components that polarise light in one plane. On the inner surface of the glass casing, transparent electrodes are placed in the shape of the desired image. The electrode attached to the front glass is referred to as the segment electrode and the one attached to the rear glass is the backplane or the common electrode. The patterns of the backplane and segment electrodes form the numbers, letters, symbols, etc. The liquid crystal is sandwiched between the two electrodes.

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An LCD controls the transmission of light by changing the polarisation of the light passing through the liquid crystals with the help of an externally applied voltage. As LCDs do not emit their own light, backlighting is used to enhance the legibility of the display in dark conditions. Backlighting is done using incandescent lamps, LEDs or electro-luminescent lamps.

LCDs have the capability to produce both positive as well as negative images. A positive image, defined as a dark image on a light background, is produced when the pixel that is ‘off’ is transparent and a pixel that is ‘on’ is opaque. In these displays, the front and the rear polarisers are perpendicular to each other.

A negative image is a light image on a dark background and is produced when a pixel that is ‘off’ is opaque and a pixel that is ‘on’ is transparent. This mode is typically used only when there is a backlight and the ambient lighting conditions are medium to dim. In these displays, the front and the rear polarisers are aligned to each other.

LCDs can be classified as direct drive and multiplex drive displays depending upon the technique used to drive them. Direct drive displays, also known as static drive displays, have an independent driver for each pixel. The drive voltage in this case is a square waveform having two voltage levels, namely, ground and VCC. However, as the display size increases, the drive circuitry becomes very complex. Hence, multiplex drive circuits are used for larger displays. Such displays reduce the total number of interconnections between the LCD and the driver. These have more than one backplane and the driver produces amplitude-varying, time-synchronised waveforms for both the segments and backplanes.

LCDs are non-emissive devices, that is, they do not generate light of their own. Depending upon the mode of transmission of light in LCDs, these are classified as reflective, transmissive and transreflective displays.

Reflective LCD displays have a reflector attached to the rear polariser which reflects incoming light evenly back into the display. Fig. 2 shows the principle of operation of reflective LCD displays. Such displays rely on the ambient light to operate and do not work in dark conditions. These produce only positive images. The front and the rear polarisers are perpendicular to each other. Such displays are commonly used in calculators and digital wrist watches.

Fig. 3: Construction of a transmissive display
Fig. 4: Transreflective displays
Fig. 5: Interfacing of LCD display with an FPGA

In transmissive LCD displays, back light is used as the light source. Most of these displays operate in the negative mode, with the text displayed in light colour and the background in a dark colour. Fig. 3 shows the basic construction of a transmissive display. Negative transmissive displays have front and rear polarisers in parallel with each other whereas positive transmissive displays have the front and the rear polarisers perpendicular to each other.

Transmissive displays are good for very low light level conditions. They offer very poor contrast when used under direct sunlight because sunlight swamps out the backlighting. These are generally used in medical devices, electronics test and measuring equipment and in laptops.


Transreflective displays are a combination of reflective and transmissive displays (Fig. 4). A white or silver translucent material is applied to the rear of the display, which reflects some of the ambient light back to the observer. It also allows the backlight to pass through. These are good for use in varying light conditions. However, they offer poorer contrast ratios than reflective displays.

LCD displays can also be classified as passive and active depending on nature of the activation circuit. Passive displays use components that do not supply their own energy to turn on or turn off the desired pixels. These have a set of multiplexed transparent electrodes arranged in a row/column pattern. To address a pixel, the column containing the pixel is sent a charge and the corresponding row is connected to ground. Passive displays can have either direct drive or multiplexed drive circuitry.

However, for larger displays it is not possible and economical to have separate connections for each segment. Also, as the number of multiplexed lines increase, the contrast ratio decreases due to the cross-talk phenomenon wherein a voltage applied to the desired pixel causes the liquid crystal molecules in the adjacent pixels to partially untwist.

Fig. 6: Flowchart for LCD initialisation

Download Source Code: click Here

These inherent problems of passive displays are removed in active displays. Active displays use an active device such as a transistor or a diode for each pixel which acts like a switch that precisely controls the voltage that each pixel receives. Active displays are further classified as thin film transistor (TFT) displays and thin film diode (TFD) displays depending upon whether the active device used is a transistor or a diode.

In both these devices, a common electrode is placed above the liquid crystal matrix. Below the liquid crystal is a conductive grid connected to each pixel through a TFT or a TFD. Gate of each TFT is connected to the row electrode, the drain to the column electrode and the source to the liquid crystal. The display is activated by applying voltage to each row electrode line by line. A major advantage of active displays is that nearly all effects of cross-talk are eliminated.

As LCD displays are not active sources of light, these offer such advantages as very low power consumption, low-operating voltages and good flexibility. However, their response time is too slow for many applications. They are also temperature sensitive and offer limited viewing angles.

LCD signals

C9F_Table_1LCD displays are available typically in 8×2, 16×2, 20×2 or 20×4 formats; 20×2 means two lines of 20 characters each. These displays come with an LCD controller that drives the display. Fig. 5 shows the interface of LCD display with an FPGA.

There are three control lines namely EN (Enable), RS (Register Select) and R/W (Read/Write). EN line is used to instruct the LCD that the master controller is sending data. It is used by the LCD to latch information present on the data pins. When data is applied to the data pins, a high-to-low pulse must be applied to the EN pin so that the LCD latches the data present at the data pins. The minimum Enable signal pulse width required is 450ns.

The RS pin is used to select the register to which the data has to be stored to. LCD has two registers to store the data depending upon its nature, namely, the instruction command code register and the data register. When the RS pin is high, data is sent to the data register. the data is a text data to be displayed on the LCD. When RS pin is low, the data is treated as command or instruction to the LCD module and is stored in the instruction command code register. When R/W pin is low, the instruction on the data bus is written on the LCD. When R/W pin is high, it means that the data is being read from the LCD. The different commands to the LCD instruction register are shown in Table I.


The 8-bit data bus is used to send information to the LCD or read the contents of the LCD’s internal registers. Sometimes, 4-bit bus is also used to send information. To display letters and numbers, we send their ASCII codes.

The software routine initialises the LCD first by setting the width of the data bus, selecting the character, font etc, clearing the LCD, turning on the LCD module and the cursor, setting the cursor position and so on. Then the data to be displayed is sent on the data lines. The different steps for driving the LCD are described in the following paragraphs.

Before using the LCD for display it has to be initialised (see Fig. 6). The LCD can be initialised either by using the internal reset circuit or by sending a set of commands to the LCD. The choice is of the designer, but the second method is more popular. The internal reset circuit is highly dependent on the power supply.

VHDL code listing
The process flow followed to drive the LCD is as follows:
1. Write 0×38, wait 4.2 milliseconds
2. Write 0×38, wait 4.2 milliseconds
3. Write 0×38, wait 4.2 milliseconds
4. Write 0×38, wait 4.2 milliseconds (function set, two-line display and 5×8 dot character font)
5. Write 0×08, wait 4.2 milliseconds (display off, cursor off)
6. Write 0×01, wait 4.2 milliseconds (display clear)
7. Write 0×0C, wait 4.2 milliseconds (display on, cursor off)
8. Write 0×06, wait for 4.2 milliseconds (shift cursor to right)
9. Write ASCII ‘W’, wait 4.2 milliseconds
10. Write ASCII ‘E’, wait 4.2 milliseconds
11. Write ASCII ‘L’, wait 4.2 milliseconds
12. Write ASCII ‘C’, wait 4.2 milliseconds
13. Write ASCII ‘O’, wait 4.2 milliseconds
14. Write ASCII ‘M’, wait 4.2 milliseconds
15. Write ASCII ‘E’, wait 4.2 milliseconds

As shown in the flowchart in Fig. 6, all steps do not require a few milliseconds for execution. However, to simplify the code, the time for all the steps is kept uniform. In case this is found unsuitable for the design, the designer can modify the timings.

Instead of using delays, one can check the status of the busy flag to see if the LCD is ready to receive information. The busy flag is the MSB of the data bus and can be read when R/W = 1, RS = 0 and low-to-high pulse is applied to the EN pin. If the busy flag is high, the LCD is busy taking care of the internal operations and will not accept any new information. When the busy flag is low, the LCD is ready to accept new information.

The VHDL code (LCD_fpga.vhd) for implementing the LCD controller is included in this month’s EFY DVD. The code writes ‘WELCOME’ on the LCD display. The LCD display used here is 16×2. One can use any display and change the initialisation commands accordingly.

VHDL code description

9C8_Table_2The code begins with the standard library to be included. The ENTITY section defines the interface between the LCD module and the outside world. It includes all the input and the output connections including the 50MHz clock (Clock) and reset (Reset) as inputs, LCD register select (LCD_RS) and LCD enable (LCD_E) as outputs, LCD read/write (LCD_RW) as buffer and 8-bit data bus (DATA_BUS) as inout. DATA_BUS is defined as inout so that it is capable for both input and output operations.

The architecture section defines the two operations of the LCD module for generating the LCD clock and implementing the FSM. The different signals defined in the architecture include state and next_command of state_type, DATA_BUS_VALUE which is an 8-bit STD_LOGIC_VECTOR, COUNT_CLK_LCD which is a 28-bit STD_LOGIC_VECTOR and CLK_LCD which is a STD_LOGIC signal. The value of the signal DATA_BUS_VALUE is ported to port DATA_BUS when LCD_RW is at logic ‘0’, otherwise the port DATA_BUS remains in the high-impedance state.

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The state_type is a signal type that defines different states of the LCD, namely Hold, Display_ON, Mode_SET, Write_CHAR1, Write_CHAR2, Write_CHAR3, Write_CHAR4, Write_CHAR5, Write_CHAR6, Write_CHAR7, Return_HOME, Toggle_E, Reset1, Reset2, Reset3, Display_OFF and Display_CLR. The state and next_command are two signals of state_type.

As mentioned before, the first operation generates the slow clock for the LCD. It uses the 21st bit of the COUNT_CLK_LCD signal; the clock signal for the LCD is named as CLK_LCD.

The second operation is the FSM that drives the LCD. If the Reset pin is in high state, the LCD is initialised by sending 0×38 in hex on the data bus. RW and RS signals are set to ‘0’ and the Enable pin is set to ‘1.’ The current state is defined as Reset1 and the next_command state as Reset2. When the Reset pin is in low state, the FSM of driving the LCD is implemented. The different states of the FSM are Reset1, Reset2, Reset3, Display_OFF, Display_CLR, Display_ON, Mode_SET, Write_CHAR1, Write_CHAR2, Write_CHAR3, Write_CHAR4, Write_CHAR5, Write_CHAR6, Write_CHAR7 and Return_HOME. Toggle_E and Hold are two sub-states.

For LCD initialisation, the command ‘0×38’ (hex) is sent to LCD in three states: Reset1, Reset2 and Reset3. It may be mentioned here that the command is dependent on the size of the LCD being used. The ‘0×38’ is used to initialise a 16×2 LCD. The RS and RW signals are set at logic ‘0.’ Enable signal is set at logic ‘1.’ The FSM is directed to sub-state Toggle_E where the Enable signal is made to go to logic ‘0’ and the FSM is directed to the Hold sub-state. The Hold sub-state directs the FSM to the next state next_command as set in the main states earlier. Remember that the data on the data bus is latched by the LCD on the high-to-low transition of the Enable signal.

After the Reset3 state, the FSM goes to the Display_OFF state. The data bus sends command ‘0×08’ (hex) to the LCD which is for display off and cursor off. The program loop then goes to the Display_CLR state. The state clears any text on the display. To do this command ‘0×01’ (hex) is sent to the data bus. The next state is the Display_ON state (display on and cursor off) which is executed by sending command ‘0×0C’ (hex) on the data bus. Next state is the Mode_SET state that sets the LCD such that the cursor shifts to right after each character is displayed. This is done by setting data bus to ‘0×06’ (hex).

The next seven states Write_CHAR1, Write_CHAR2, Write_CHAR3, Write_CHAR4, Write_CHAR5, Write_CHAR6 and Write_CHAR7 display seven alphabets ‘W’, ‘E’, ‘L’, ‘C’, ‘O’, ‘M’ and ‘E’ on to the display. The next state is RETURN_HOME that sets the address of the next command to be written and then sends the FSM to the Reset1 state. ‘WELCOME’ is again written on the LCD and the process is repeated again.

It may be mentioned here that the default position of the cursor is the beginning of the first line. If any other position needs to be used to display the text, a command needs to be sent to force the cursor to the desired position. Table II gives the addresses of different positions of the LCD.

This part described the LCD controller implementation using an FPGA. The next part will cover details on how to establish an RS-232 communication link using an FPGA.

Varsha Agrawal is a scientist at Laser Science and Technology Center (LASTEC), a premier DRDO lab working in the field of laser-based defence systems. She has more than 13 years of R&D experience in the design and development of a variety of systems for defence-related applications. She has authored two books and published more than 20 research papers and technical articles