PHY is an abbreviation for physical layer of the conceptual open systems interconnection (OSI) model. With ever increasing demand for faster data transfers, over the recent times, the demand for hi-tech electronic products has considerably increased in India. Especially with introduction of the concept of the Internet of Things (IoT), where every device is connected to each other and to the Internet, there is growing need for enabling high-speed, high-throughput and high-performance systems.

Terminus Circuits Quad Lanes PCIe 3.0 PHY_10Gbps Multistanard SerDes Hard IP solution
Terminus Circuits Quad Lanes PCIe 3.0 PHY_10Gbps Multistanard SerDes Hard IP solution

The multi-standard 10Gbps SerDes offered by Terminus Circuits is an off-the-shelf intellectual property (IP) offering that forms part of a main system-on-a-chip (SoC) or high-end equipment manufactured and sold by original equipment manufacturers (OEMs). It was designed and developed by K.S. Sankara Reddy, founder of Terminus Circuits, and his team in 65nm general-purpose (GP+) technology.

It is a PHY product that can support channels up to 32dB of attenuation, covering most of the cables supplied by the cable vendors. This multi-standard SerDes supports standards like serial ATA (SATA), serial attached SCSI (SAS), XFI, 10GBASE-KR, Peripheral Component Interconnect Express (PCIe) and universal serial bus (USB). This product forms the heart of high-speed and high-throughput servers.

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The device is suitable for complex applications like weather forecast, brain simulations, high-performance computing (HPC), cloud computing and network operations centre (NOC). It can also act as enabler for SoCs targeting the latest standards like SuperSpeed and SuperSpeed+ USB (USB 3.1), PCIe 4 and applications like solid-state drives with native PCIE, terabytes routers, etc.

Design elements
The analogue part of the transceiver is the physical medium attachment (PMA) that comprises custom-made transistors with a QUAD configuration for attaining high throughput (up to 40Gpbs). The clocking solution consists of three individual phase-locked loops (PLLs) that support data rates and standards ranging from 2.5Gbps to 10Gbps.

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The digital side of the product, like Physical Coding Sublayer (PCS) and MAC (Media Access Controller) layer, consists of 500,000 standard cells connected for controlling and enabling the device connectivity between digital and analogue worlds, thus making the complete system that meets the standards mandated by various committees like USB.org, PCI-SIG, SATA, IEEE and SerDes.

The innovative design of this SerDes would help the OEMs in reducing the number additional off-the-chip components, such as high-precision resistors, clocking solutions and current-bias circuits. The complete solution is built on monolithic silicon as a single block. Thus the reduced number of external connectors and packaging complexities simplifies the test solution and reduces overall size, cost and power consumption of the system.

This SerDes is a specification-driven product that needs to meet stringent requirements of high-speed interface technologies. Its innovative transistor-level circuit design is key factor for the optimal solution that provides low power, high performance, cost saving for applications that meet customers’ expectations. It comes with built-in PLLs designed for 10GHz frequencies for clocking solutions. A non-chip, high-precision bias current generator in the design helps to reduce the necessity for multi-chip modules or single-module solution with clocking, data transfer and multiple bias generators.

Design challenges
It took almost three years to claim the finished SerDes IP design. Currently, there are only a handful of companies across the globe that provide such high-speed SerDes IPs. The product is first of its kind developed completely in India and meets the requirements prescribed by the standards bodies like IEEE, USB.org and PCI-SIG.

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The complexity of the design being very high, its development required manpower that had years of experience in designing SerDes IPs and their sub-blocks. Scarcity of highly knowledgeable, skilled and experienced workforce in this field was a challenge.

The product has received the ‘Most Innovative Product of the Year 2013’ award from India Electronic and Semiconductor Association (IESA) in recognition of innovative ideas that were implemented in the design of SerDes, which helped the customers to mitigate their SoC and package complexities.

This is a finished product that can be readily adopted by fabless design houses or OEMs. These products are offered through flexible licensing, royalty or buyout options. It can be sourced to customers worldwide through the web portal Design & Reuse (D&R). The IPs can also be picked up by OEMs who intend to do fab-out of their designs through foundries like Taiwan Semiconductor Manufacturing Company (TSMC), GlobalFoundries and Integrated Device Manufacturer (IDM).


The author is a dancer, karaoke aficionado, and a technical correspondent at EFY. Find her on Twitter @AnuBomb.

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