Electronics revolution has been a very interesting one. You have lightning fast connectivity, crystal clear displays, blazing fast processors, all in a handheld device. A major part in the device however has been the silicon. With recent mishaps, resulting in full page apologies, safety also becomes important. Proper testing is the only way to ensure that the device you have does not go kaboom, anytime. Let’s look at how semiconductor tests make them for the better.
A look at the process
An Automatic Test Pattern Generator (ATPG) takes the design and creates a list of the faults that need to be tested. Robert Ruiz, sr. product marketing manager, test automation, Synopsys Inc., explains, “To test a silicon die, you feed ‘0’ and ‘1’ into the silicon.” The probes in the test setup, touch certain places on the silicon and push in these values. Then it runs the clock of the chip and taking the values up. “If the chip is perfectly fine, the output is as expected. We know what the good output is going to be, since we set it” said Ruiz.
Gal Hasson, sr. director marketing, RTL synthesis, test automation, Synopsys Inc., adds, “What ATPG does is for each potential defect, it creates inputs. If a certain point is defected, the output is going to be different than the output of a good chip”. The use of probes is also becoming redundant with time. Hasson adds, “Using probes in the middle to measure parameters are some old techniques. The designs have been modified to be more testable”. Basically the ATPG tool can put values on the outside and propagate them in a way it pretty much however.
Why test silicon?
Testing has become very important with today’s number of devices. The adoption of FinFET nodes has been on the rise. We are seeing a constant rise in tapeout for 16/14nm designs. Higher quality in automotive is also essential. The demand is now for less than 1 defect per million parts. Also, a lot of defects can not be found with standard methods.
Some of the general test and quality trends have been along the lines of high design complexities. Due to the higher complexity of designs, there is a need for similar test procedures. Increasing patterns vs process node has resulted in higher silicon test costs. Longer delays to test silicon have to be reduced, resulting in the need for faster tapeout. High ATPG memory consumption, limits the number of cores being utilized.
On the other hand, testing every inch of silicon is going to increase the costing as well. If a manufacturer can reduce their costs, it is an added plus. Reduce the costs significantly, you could possibly have the cost of an IC down by a major margin. And next gen tools do just that. “A manufacturer can either go for the quality while increasing the costs or they can opt for lower quality while testing and save on the testing.” added Hasson.
Where’s the need?
Today we have the requirement from automobile industry for BIST in silicon as well. Ruiz explains, “Not just in memory, but in the logic design as well”. In safety critical parts, a car for example, the electronic components should be tested and working properly. “If there is no problem, bring it back online and test something else”. Makes it easy to raise a flag. In case something is wrong, you can get it serviced before disaster strikes. Automotive is however just one of the areas. Safety critical applications require to be tested on a regular basis, and tools that can provide testing in field environments are a big step in the direction.
New testing system features
Extremely high capacity and performance are just the tip of the iceberg. The latest test software include support for multi-core systems for accelerated run time. Integrated graphical user interface, hierarchy browser and simulation waveform viewer add to the set of features. Such features not only add to the ease of use but also allow quicker and efficient functioning. In testing you have to find the factors contributing to the problem.
“You have to profile and find out the bottlenecks and paralyse them. You check again and you see that the problem moved around and so on,” explains Ruiz as one of the areas of fine grained multi-threading. “The earlier system used to check for the faults serially.” says Ruiz. However the current systems look at all the faults and generates the input and output values to detect each one of them separately.
Compression design rule check (DRC)
DRC determines if physical layout of a particular chip satisfies a series of recommended parameters. It is a major step during physical verification signoff on the design. Design rules are specific to a particular semiconductor manufacturing process. Design rule checks do not necessarily validate the design operation. They are constructed to verify that the structure meets the process constraints for a given design type and process technology.
The latest softwares identify chip-level test issues. Violations can even be analyzed by viewing directly on the circuit. Detailed violation information is available with context-sensitive help. These softwares also support full scan and partial scan test methodologies using mux-scan, clocked-scan, level sensitive scan design (LSSD). Support for designs with IEEE 1149.1/6 internal scan shifting protocols and related techniques are an additional plus.
Post fabrication, you have a wafer, which has on it multiple die. Some of them are defective, while many are not. Identifying the defective parts is kind of a big deal. The good ones go to the market to be sold, whereas the defective ones are trashed.
In addition to identifying defective parts from manufacturing, test software can also isolate the location of defects on devices failing test patterns. Automatic and accurate defect isolation is an important step to diagnose critical yield issues, both during production ramp as well as in volume manufacturing. They also report the fault candidate locations that most likely explain the faulty device behavior observed on the tester. Current diagnostics use advanced heuristics and a high-performance fault simulator for rapid and reliable results in a volume manufacturing environment.
Plethora of tests: one little chip
DRC is just a broad way to cover the numerous checks a silicon die goes through before assembly and packaging. However, testing does not stop there. After testing, it again goes through tests to check for any errors in implementation and short circuits. I genuinely wonder if a silicon die passes more signal tests than circuit implementations.
I have a newfound respect for silicon
A piece of silicon goes through so much in it’s lifetime to get it right. Once it does get everything right, it either ends up in a lab or is implemented in a circuit by some manufacturer.
If it goes to the manufacturer, it’s alright. But if it ends up in a lab, it might end up with a rookie or the hands of a professor.
If the professor handles the silicon, it’s alright. But if it ends up with the rookie, they can either break it’s pins or handle it properly.
If they handle it properly, it’s alright. But if they break its pins, they can either throw it away, or tell the professor they broke it. Let’s be honest for a second, nobody tells the professor. It’ll be thrown away.