Fast-track Evaluation And Prototyping

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With the advent of technology in the growing US$ 5 billion field programmable gate array (FPGA) market, the board and the system computing shrank from a single-board computer to a system on chip (SoC). Developing a new mask, or circuit pattern, to upgrade a single chip can cost US$ 2 million to US$ 5 million.

As a consequence of missing product cycles, issues related to technology or design come up that cost a dear to the revenues. End users often have to replace equipment or endure sub-optimal performance because of unanticipated in-field conditions. Modems need to be reconfigured for various processing schemes of communication and digital signal processors (DSPs) or other processing tasks that require hardware acceleration.

With these reasons, FPGA paired with a custom chip is a great idea. The ultimate point of making a custom chip is to integrate and consolidate. Essential features of the FPGA are good performance, smallest form factor, lowest power consumption and lowest bills of material (BOM) cost.

This technology puts some FPGA fabric in the custom chip design. Customers do not require any FPGA expertise to use the technology. If one customer needs pins for X and another customer needs for Y, he or she can do it in-code with existing chips. To enable customers to do hands-on evaluation, embedded flexible (EFLX) will make available free, under the encrypted Verilog model, LIB, LEF and detailed datasheet of EFLX core.

EFLX blocks can be used anywhere in the chip—connected to RAM and input/output (I/O), used in the data path or on the processor bus. But FPGA companies do not offer their fabric as intellectual property. FPGAs require many metal layers to achieve routability, which is needed to make these useful. If the device does not include many layers, it would take a major and expensive upgrade of design to handle the overhead of adding conventional FPGA fabric to the mix.

But the so-called EFLX technology is based on programmable logic with RTL reconfigurability. EFLX technology allows SoC designers to embed FPGA into complex chip designs. Applications such as encryption, networking and signal processing require blocks of RAM to be integrated into the FPGA to provide fast local memory to implement buffers, scratchpads, FIFOs and other low-latency memory that improves performance.

EFLX is a fully-functional FPGA. Instead of existing in systems as a standalone chip, it is integrated into communications chips, microcontrollers (MCUs) and other devices. The technology is scalable for larger designs. Larger EFLX cores could easily be developed to support array configurations over 300k gates.

EFLX has developed a new and novel type of hierarchical interconnection network that can cut interconnect resource requirements by 50 per cent or more, reducing the number of metal layers required. At the same time, the more efficient interconnect reduces power consumption, improves performance and makes timing closure easier. Hardware design is fast but fixed, while software like operating systems or apps can be easily changed. It provides licences for its technology to chip makers who can embed EFLX hardware into their own designs. Wireless networks could get speed upgrades sooner, or Internet services like search engines could be upgraded with new features.

Typical applications include fast control logic, intelligent I/O crossbars, customisable DSP accelerators, logic blocks to support many market segments or customers with a single chip, reconfigurable base-station digital front-ends, programmable parsers, reconfigurable protocols and more. EFLX can provide a ton of I/Os—632 per direction per tile in a 7 x 7 array that adds up to big numbers even after tile-to-tile and memory interconnects. In the MCU segment, EFLX blocks can be configured as something that amounts to a smart crossbar.

EFLX, a fully-functional FPGA

EFLX FPGA has parallel data paths running vertically and interfacing to peripherals laterally such as the advanced extensible interface AXI Slave, which connects to ARM advanced MCU bus architecture. Basic part is an FPGA; interconnect and I/O block is called EFLX-2.5K when built on TSMC 28HPM. The 28nm high-performance mobile (HPM) computing provides high performance for mobile applications to address the need of applications requiring high speed. Such technologies can provide the highest speed among 28nm technologies. It gives implementer 2520 LUTs, 5040 flip-flops, eight clocks, 632 inputs and 632 outputs.
The second variant is called EFLX DSP core, and its main addition is a DSP block.

EFLX blocks can be used anywhere in a chip for connection to RAM and I/O, in the data path or on a processor bus. It can integrate any kind of RAM of any width, size, having single or dual port, ECC, parity or neither. Memory can be put between cores and controlled with unused I/O.

EFLX memory compiler maps RTL code onto the array including RAM. EFLX blocks are programmed with RTL. Both architectures can be tiled together in up to a 7 x 7 array, and, if needed, provide GDS, LIB, LEF and Verilog files. The incremental die cost is less than five cents per k-input-look-up tables (k-LUTs), which is much less than packaged FPGAs.

If memory is needed, interconnects between the tiles can have DRAM blocks added to these. Instead of wiring up I/Os from one tile to the next directly, memory is placed between tiles, and I/Os on the periphery of the tile group take over I/O duties for the entire set.

28nm is the first generation that foundry industry starts to use high-k metal gate (HKMG) process, which represents TSMC. Still, poly/oxnitride process is offered to meet customers’ time-to-market need. It is ideal for low standby power applications such as mobile baseband. In a 28nm process, fast control logic can run at 525MHz or more, and pipelined finite impulse response filters (FIRs) can run up to 450MS/s or faster.

SSG corner signoff provides 10 to 15 per cent performance boost over 28HPM SS corner signoff
Fig. 1: SSG corner signoff provides 10 to 15 per cent performance boost over 28HPM SS corner signoff

In 40nm, multiple speed/power tradeoffs are supported to address almost all possible requirements. The 28nm low-power with high-k metal gates (HPL) technology adopts the same gate stack as HP technology while meeting more stringent low-leakage requirements with a trade of performance speed.

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