As we advance from one generation of technology to the next and develop smaller, faster and more functional chips, there are key inflection points where innovative technologies must be developed. This interview discusses the key emerging technologies in the semiconductor space, including an alternative to Silicon itself.
Dr. Randhir Thakur, with over 300 patents and more than 200 papers published, was named an IEEE Fellow in April 2013 for his ground-breaking leadership in development and implementation of single-wafer technology in semiconductor manufacturing. In an interview, Abhishek Mutha of EFY talks to Dr. Thakur, Executive Vice President and General Manager of the Silicon Systems Group at Applied Materials, Inc., about inflection points driving today’s semiconductor industry, the evolution of the process to make microchips and why single wafer solution and how he revolutionized his vision on single wafer technology.
Q. What are the key inflection points that designers should be aware of?
A. As the industry moves from one technology generation to the next to make smaller, faster and more functional chips, there are key inflection points where innovative technologies must be developed to meet new manufacturing challenges. There are several key inflections that we are encountering today. Among these are:
Transistor: The transistor which is effectively the on-off switch of each device is incredibly complex and so small that billions of transistors are run on microchip architectures. And they are getting more complex and smaller. However, to make these transistors work reliably at the more advanced technology nodes, new materials and designs are needed.
Patterning: To pack billions of transistors on today’s most advanced microchips, manufacturers must seemingly defy the laws of physics, using complex lithography methods to print, or “pattern” the wafer with chip features that can be a thousand times smaller than a human hair.
Interconnect: Interconnects are the electrical pathways that connect transistors and other circuit components to one another – and to the outside world. They are critical to the speed and reliability of a microchip. Because modern microprocessors can have as many as ten levels of interconnects, this intricate structure is one of the most process-intensive – thus most costly – portions of the total chip fabrication process.
Packaging: An emerging area for Applied Materials’ technology is in three-dimensional integrated circuits (3D-ICs), a type of chip packaging done at the wafer level to streamline the manufacturing process. In a 3D-IC, multiple chips are vertically stacked in a single package to deliver higher performance and functionality in a smaller area. The chips are electrically connected using deep holes called through-silicon vias (TSVs).
3D NAND Memory: After following Moore’s Law for nearly 40 years, increasing the storage capacity of traditional, two-dimensional memory chips by decreasing the size of its features, called “scaling,” is becoming very difficult. For example, an advanced 25nm flash memory chip stores each bit of information using approximately 100 electrons. Containing those electrons reliably over millions of read/write cycles is a major challenge – and achievement.
Q. As integrated circuits become more complex, how is Moore’s law being kept alive?
A. The persistent need for higher performance with lower power computing within consumer devices has ensured that our customers continue to keep Moore’s law alive. This constant advance demands that the equipment which enables node scaling must also evolve.
As integrated circuits have scaled, they have become increasingly complex. Today we are seeing novel 3D device architectures emerging and replacing historical 2D planar device architectures. 3D has become a fundamental shift, spanning advanced logic, memory and packaging.
While enabling transistor-level performance is a key driver for new materials and process equipment, the need for ensuring low power has also meant that the ever increasing layers of on-chip metal interconnect be more power efficient with techniques such as low-ohmic contacts at vias and insulating the interconnect with advanced low-k dielectric materials. For the same high performance with low power target, we’re also starting to see the inception of advanced packaging techniques. Producing these more complex structures on a silicon wafer has increasingly become a challenge of materials engineering, advanced patterning techniques, and ensuring high yield in a high-volume manufacturing environment.
Hence tools have evolved to be able to selectively deposit or remove a wide variety of materials previously unknown to semiconductor processing. There is also an increasing need for better unit process integration, which has driven the emphasis on cluster tools, whereby a wafer surface is not exposed to ambient conditions between process steps.
Such technology drivers have meant that single-wafer solutions are best suited for sophisticated demanding process steps. Batch is still used in commoditized process steps which are not critical for fine feature-size based node scaling, such as wet cleans. However they encounter severe limitations in ensuring highly precise nano-scale features.
Q. What are the challenges faced while moving to the single wafer technology?
A. As with any major cross-industry shift, there were indeed many challenges. A major aspect is to ensure tool readiness that is exactly in sync with the customer’s technology roadmap. Tuning a company’s long-term R&D effort to perfectly time with a major inflection is in itself a major challenge. So one can only imagine needing to engage the entire equipment supply chain in a highly collaborative R&D effort to drive towards the new tool standard. We needed to actively manage the risk of the migration to a newer industry standard on multiple fronts, such as technology, architectural changes such as wafer handling systems and financial R&D planning, etc.
But more than any other factor, ensuring the availability of a solution that provides a significant improvement in on-wafer performance with low risk was essential to get customers to adopt the new single-wafer standard on a significant enough scale.
Q. You did your Ph.D. on In-situ Integrated Rapid Thermal Processing of Advanced Materials and Devices. How has the adoption of RTP technology in dynamic random access memory (DRAM) integrated circuits helped today’s electronics industry?
A. What the adoption of RTP enabled is basically scaling DRAMs below the 0.6 micron technology node. Today the industry is scaling to the 25nm node. Once proven in DRAM manufacturing, RTP was adopted in the manufacture of other devices such as logic, non-volatile memory, analog and MEMS. Today, single RTP is a fundamental enabling technology in the fabrication of the most advanced semiconductor devices.
Q. Could you give us an insight on the emerging technologies in the semiconductor industry?
A. The next 5 years are expected to see more technology inflections and shifts than the past 15 years. A major inflection starting to play out now is the fundamental shift to 3D device architectures – such as finFET in the logic space, and 3D NAND in flash memory. Realizing these complex structures requires more process steps, to selectively deposit or removal material with highly repeatable precision in a volume manufacturing environment.
On a longer-term horizon, we can expect to see the 450mm inflection, during which the wafer-size standard moves from 300mm (12”) diameter to 450mm (18”). We’re currently in the R&D stage of developing tools for the 450mm wafer standard.
Q. Silicon is almost always used in designing and manufacturing ICs. Is there any research being done on alternate material?
A. As mentioned, tools have evolved to be able to selectively deposit or remove a wide variety of materials previously unknown to semiconductor processing with very high levels of precision.
In terms of the substrate itself, there is quite a lot of fundamental research ongoing in academia. A good example is the usage of Graphene as a basic substrate material. There are certain process steps in packaging schemes (such as interposers) where glass can be considered as an alternative to silicon.
Nevertheless, the well understood electrical and physical properties of silicon handling, and the economics of processing, make us believe that silicon is to remain the mainstay substrate material of choice for quite some years to come.
Q. Congratulations on your recent career achievement on becoming an IEEE Fellow. Would you like to share your thoughts on that?
A. It is certainly a prestigious honor and I am very humbled to receive it. I consider it as one of the highlights of my career, and I’m pleased to have been able to make a meaningful contribution to the industry. It’s gratifying to know that my work on the development and implementation of single-wafer RTP technology has led to key improvements in device performance and manufacturing cycle time.