Numerous developments have happened in the EDA world – vendors come together to support a single standard, technology that allows you to reduce power consumption, and a shift towards cloud-based EDA tools. This interview gets you up to date on all of these, and finally answers your question on whether you should simulate or emulate your next design.
Raghu Panicker, Country Sales Director, Mentor Graphics spoke to Ashwin Gopinath about the company’s efforts to standardize verification methodologies and the differences between emulation and simulation.
Q: What does a design engineer need to know about Universal Verification Methodology (UVM), the new methodology where a lot of investment is happening?
A. Earlier, there were 2 hardware languages, Verilog and VHDL. Over time, the ICs have changed a lot from the FPGA to today’s SoCs, which is essentially, an entire system on a chip. This indicates that a lot of ICs have come into use on a single chip. With that, the hardware is now to be viewed more like a system leading to the newer language called system Verilog, which means you now have to visualise things in a system format. Now when it came to that segment, various standards came in and EDA vendors were driving these standards. Almost every major vendor had their own unique standard that was crowding the market with non-uniform standards. That’s when we and a couple of other semi-conductor companies came together and constituted a board that would look at newer standards. The result is Universal Verification Methodology, which was adopted to take care of system Verilog concepts and features, and is a standard adopted by multiple simulation vendors.
Q: What are the key differences here between emulation and simulation in the EDA world?
A. On a very basic level, emulation is nothing but heavy-duty regression that happens when you run a design through it. Generally, on a system, there is a limit to which you can use a simulator to run a fixed-design. When this limit is breached, the cost becomes so prohibitive that you cannot reach that speed using simulators. Hence, you need an emulator to emulate that kind of functionality and hence, we go for emulators. As the design size increases, emulating those functionalities in an emulator becomes the key.
Q: What is the cost analysis for design houses when they decide on emulation vs. simulation?
A. More than just cost analysis, the time-to-market is seen as the dominant factor. In an emulator system, you cut down the time by almost one-tenth, which is a huge advantage. If you run a regression with a simulator, it will take four to five days on a specific design. But if you can cut down the time from a couple of days to mere hours, that’s a much bigger advantage than the cost savings. Emulators obviously cost much more but they more than make up for it by cutting down the time by up to a third on the front-end alone.
Q: So when should a designer use an emulator rather than a simulator?
A. A designer would prefer an Emulator rather than a Simulator when he finds the following benefits:
• Improves end product quality by increasing the total verification cycles on the design before committing to silicon prototypes.
• Reduces silicon spins due to functional problems by enabling full-system integration testing before first silicon.
• Moves software off the project’s critical path by allowing debugging on emulated hardware early in the design process.
• Improves ROI by becoming the verification hub for simulation and emulation of SoC designs.
• Scalable verification platforms with capacities from 16 million to 2 billion gates.
• Simulator-like debug environment.
• 100% internal DUT visibility.
• Network accessible, multi-user systems.
Emulator hardware and software solutions allow design teams to quickly create reconfigurable hardware representations of new SoC designs and leverage verification investments across the project. This reduces the risk of design flaws in pre-silicon testing by verifying the SoCs compliance and interoperability with industry-standard protocols, thus reducing overall project schedules and costs.
Q: What technologies are available for design engineers to achieve lower power consuming designs?
A. Designing for low power is very critical. Let’s take a laptop as an example. You wouldn’t want it to consume the same amount of power while sleeping as when it is doing heavy work. So, what is done is that, through Multi-Corner, Multi-Mode (MCMM) technology, we take care of all these options in one shot, under all these conditions. Basically what happens is, at a certain time, it operates at a certain voltage, at other times, other voltages – this creates a large number of options. We take care of all these options and do Place and Route for them. This is something that has to be taken very seriously, and work and investment in this area has been there for a while now.
Q. Could you elaborate on how MCMM technology helps designers lower power consumption of their systems?
A. The Multi-Corner, Multi-Mode (MCMM) capability engine concurrently computes delay shift and glitch for any number of mode/corner scenarios in a single pass. MCMM analysis enables customers to address reliability issues such as crosstalk delay, glitch, power, and electro-migration while reducing the time to achieve design closure. Customers designing at lower nodes are experiencing a significant increase in SI related timing violations due to increasing dominance of lateral wire capacitance. An explosion in the number of mode and corner scenarios that must be addressed exacerbates the problem, significantly increasing the time to design closure. Current solutions are severely limited due to inability of the core STA engines to represent more than a single mode/corner combination for SI analysis. This severely hampers design teams who are forced to run several iterations with a lot of manual intervention.
Q: What is your level of involvement with Indian start-up design houses?
A. We take a lot of pride in making sure that we address the startup market in a unique way. What we have realised after working with some of them is that, the two major factors which contribute in a big way is the manpower cost and the infrastructure cost. Now, the infrastructure cost could be the tool cost, machine cost or the NRE cost. Over a period of time, we have realised that when a new startup comes up, if in a way we could take care of them until they get their first prototype out, that gives them a larger success in front of their VPs and customers. So, we ensure that we give them the tools, free of cost until that time period. So, that’s the first big step that we have taken in the last couple of years. .
After the proof of concept is done, there are VCs that come and fund, we run a program called “terms for startup”, which includes a period of 12-18 months where they productise the entire proof of concept that they’ve come out with. During this time, we offer them the tools at a highly discounted rate with a very good payment plan so that the tools are available to them for the product design. These are the 2 ways we help through our side. We work closely with startups to synergise their growth efforts by partnering with them from the initial stage itself. This is very unique to the Industry and has helped us to catalyse the growth of many startups in India. We are trying to build this ecosystem so that the entire Industry is benefitted going forward. India is a big growth market for many startups and we definitely want to play a significant part in this journey.
Q: What are Mentor Graphics’ thoughts on “EDA on Cloud”? Do you think this migration to the Cloud will make EDA affordable for the smaller independent design houses?
A. EDA on Cloud is an interesting concept. Mentor is testing internally to see how this will work in a sense that there are IP issues/challenges that may come up. From the internal side of things at Mentor, we are trying to see this will work in its entirety. You have to let out your design, the design goes to some place, undergoes processing and then you get the results. There is a fair amount of skepticism from the semi-conductor companies because they have to let go of their IPs and designs. Now, we are waiting to see what do we need to do to lessen the negativity surrounding this. I know for a fact that one of the companies in the UK is working with their customers to see how this concept works. It is still a technology under the covers as of now. It is a little early in the day to comment on whether this will disrupt the market, and how.