Numerous developments have happened in the EDA world – vendors come together to support a single standard, technology that allows you to reduce power consumption, and a shift towards cloud-based EDA tools. This interview gets you up to date on all of these, and finally answers your question on whether you should simulate or emulate your next design.
Raghu Panicker, Country Sales Director, Mentor Graphics spoke to Ashwin Gopinath about the company’s efforts to standardize verification methodologies and the differences between emulation and simulation.
Q: What does a design engineer need to know about Universal Verification Methodology (UVM), the new methodology where a lot of investment is happening?
A. Earlier, there were 2 hardware languages, Verilog and VHDL. Over time, the ICs have changed a lot from the FPGA to today’s SoCs, which is essentially, an entire system on a chip. This indicates that a lot of ICs have come into use on a single chip. With that, the hardware is now to be viewed more like a system leading to the newer language called system Verilog, which means you now have to visualise things in a system format. Now when it came to that segment, various standards came in and EDA vendors were driving these standards. Almost every major vendor had their own unique standard that was crowding the market with non-uniform standards. That’s when we and a couple of other semi-conductor companies came together and constituted a board that would look at newer standards. The result is Universal Verification Methodology, which was adopted to take care of system Verilog concepts and features, and is a standard adopted by multiple simulation vendors.
Q: What are the key differences here between emulation and simulation in the EDA world?
A. On a very basic level, emulation is nothing but heavy-duty regression that happens when you run a design through it. Generally, on a system, there is a limit to which you can use a simulator to run a fixed-design. When this limit is breached, the cost becomes so prohibitive that you cannot reach that speed using simulators. Hence, you need an emulator to emulate that kind of functionality and hence, we go for emulators. As the design size increases, emulating those functionalities in an emulator becomes the key.
Q: What is the cost analysis for design houses when they decide on emulation vs. simulation?
A. More than just cost analysis, the time-to-market is seen as the dominant factor. In an emulator system, you cut down the time by almost one-tenth, which is a huge advantage. If you run a regression with a simulator, it will take four to five days on a specific design. But if you can cut down the time from a couple of days to mere hours, that’s a much bigger advantage than the cost savings. Emulators obviously cost much more but they more than make up for it by cutting down the time by up to a third on the front-end alone.
Q: So when should a designer use an emulator rather than a simulator?
A. A designer would prefer an Emulator rather than a Simulator when he finds the following benefits:
• Improves end product quality by increasing the total verification cycles on the design before committing to silicon prototypes.
• Reduces silicon spins due to functional problems by enabling full-system integration testing before first silicon.
• Moves software off the project’s critical path by allowing debugging on emulated hardware early in the design process.
• Improves ROI by becoming the verification hub for simulation and emulation of SoC designs.
• Scalable verification platforms with capacities from 16 million to 2 billion gates.
• Simulator-like debug environment.
• 100% internal DUT visibility.
• Network accessible, multi-user systems.
Emulator hardware and software solutions allow design teams to quickly create reconfigurable hardware representations of new SoC designs and leverage verification investments across the project. This reduces the risk of design flaws in pre-silicon testing by verifying the SoCs compliance and interoperability with industry-standard protocols, thus reducing overall project schedules and costs.