“An SoC is like a set of Lego Blocks”

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EDA is providing the enabling technologies and infrastructure that help foster innovative SoC designs. The innovation in EDA itself has also led to the combination of more processes and new IP to create next-generation designs.

Dilin Anand and Sneha Ambastha of EFY spoke to Dr. Ajoy Bose, Chairman, President and CEO, Atrenta Inc. and Sushil Gupta, Vice President and Managing Director, Atrenta India about the EDA industry and the importance of RTL signoff. Read further to find some interesting facts about the usage of SpyGlass in the EDA design flow.


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Dr. Ajoy Bose, Chairman, President and CEO, Atrenta Inc.

Q. What are the three most important challenges that are tackled using EDA tools?
A. There is a large ecosystem of IP that spans everything, created by large companies like ARM as well as other smaller firms creating IP for various applications such as cameras, video processing and various types of wireless applications such as Bluetooth, wi-fi and the like. Integrating these functions is one thing that EDA enables for system-on-chip, or SoC design.

Companies now design SoCs based on 28nm and below semiconductor processes. The thing that drives the SoC is the technology node and these technology nodes bring benefits of higher density, higher performance and lower power.

The third driving force for SoCs is the all-important economics of the chip. The cost of developing an SoC has become very expensive. There are creative ways to design a less expensive chip, however. In this complex industry, depending on who you are and where you are in the chip eco-system, you may have different priorities. People that are creating hand-held devices are more concerned about power, while those who are creating wired applications are more concerned about performance. On the other hand, anything linked to the consumer industry has a time to market pressure because the consumer market is very cyclic. EDA plays an important role here in providing enabling technologies and infrastructure to help put the IPs together and create an SoC that meets the time to market, power, performance and cost requirements of the application.

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Q. What is the most preferred technique to offset chip complexity, which increases with every functionality added?
A. There are a number of techniques and probably the most common technique is to utilize a higher level of abstraction. In a way, an SoC is like Lego blocks (a child’s game) where the blocks are assembled together. In today’s world, when there are hundreds of millions of transistors used in a single chip, analyzing and optimizing the design at the transistor or at gate level is very difficult. There is just too much data. If we consider the IP blocks of the design things become easier. Using this level of abstraction – IP blocks at the register transfer level (RTL), it is much easier to process the data and make changes. It can be an order of magnitude faster in many cases. These IP blocks can be thought of as the Lego blocks that must be assembled efficiently.

Q. Are there any innovative/out-of-the-box enhancements making their way here?
A. Two items come to mind. First, the reuse of very complex IP blocks, called subsystems. Thanks to well-defined interface protocols, large-scale blocks can now be interfaced easily, bringing the abstraction level even higher. The second is more efficient use of design hierarchy. Using the design hierarchy correctly lets you “divide and conquer” complexity. For example, you need only check the internals of a block once and then use it many times in the chip, each time only checking the interface and not the internals over and over again.

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Q. Could you elaborate on the importance of RTL signoff process?
A. If you look into the trends in SoC design, one of the key points is to select IP blocks that have high quality, are robust and provide you with the functionality you need. Atrenta’s SpyGlass analyzer plays an important role in this early IP block selection process. We have a set of functions that we offer to our customers that help them to analyze the overall quality of the IP block. Analyzing the block means predicting the cost, power consumption and performance of the block and how it will function in the SoC.

So the first analysis takes place at each block and then a similar analysis is performed at the full SoC level when all the blocks are put together. We are able to predict the cost, performance and power consumption of the design before it is actually implemented in detail. We call this process RTL signoff. Then comes the role of the major EDA tools that are provided by the big players like Cadence, Synopsys and Mentor for detailed implementation. From there the SoC is taken to the fabrication level.

Q. What is the key differentiator here compared to conventional tools?
A. The key differentiator is that they work at a much higher level of abstraction, called RTL. At the early level of design we can predict things like power, performance and cost before the expensive and time-consuming process of detailed implementation begins. Designers can make decisions early and optimize the design so that the rest of the process has a smaller number of iterations and is more cost-effective.

Q. In the initial stages after the development of the SpyGlass analyzer, Atrenta would have faced many challenges to bring this tool into the market. What were those challenges and how did Atrenta convince your customers and overcome these challenges?
A. First of all, people do not like change. They like to do things the way they have been, so yes, part of our journey has been a missionary process. There were two things that happened that helped us. One is that our technology got better and better so the results were more dramatic. The second was that the problems got worse and worse. We have benefited from the fact that the world of design has moved from 130 to 90 to 65 to 45 to 28 nm. At every step the ability to do early prediction of power, cost and performance helps us to grow. These parameters play a very crucial role in the success of an SoC project. It took some time for us to get to this point and today we have become a “de facto” standard. Every company is using us and people are requiring their partners to adopt SpyGlass as well.

There are several factors that helped us to convince our customers to buy SpyGlass. If a problem that can cause chip failure is detected at an early stage, a lot of wasted effort can be prevented. In consumer products, the design cycle plays a very important role and if a company misses a market window, the product may not even be relevant in the market. So people started becoming a big believer in SpyGlass if they experienced problems that caused schedule delays.

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Q. When you say RTL signoff is a significant differentiator, how do you define a differentiator here?
A. RTL signoff is a kind of fundamental capability to verify your requirements at the early stage of design analysis, which was not possible before due to a lack of tools. This makes it a significant differentiator because it allows one to identify and fix problems early. It gives you improved time to market and lower cost. Atrenta’s uniqueness in offering this capability has set us up in the EDA eco-system as a powerful company. The industry has been dreaming about RTL signoff for the last 15-20 years and it is now becoming a reality and we are helping to make it happen. There is no other company that provides all the tools required for RTL signoff.

Q. Until the advent of SpyGlass and RTL signoff, how was the analysis done?
A. In the early days when SpyGlass was not available, chip analysis was done in the later stages of implementation which made it much more expensive and difficult due to complexity.

Q. Are there any new techniques to overcome power leakage here?
A. Atrenta focuses on the early stage of design – before traditional EDA tools are used. In this domain, there are several approaches to reduce leakage power. You can create power domains and literally switch off parts of the chip that are not in use. You can also modify supply voltage – lower voltage means lower leakage. And, for memories, you can enable something called “light sleep” mode, which reduces power but allows the memory to turn on quickly when needed.

Q. We have seen some EDA companies setup their tools to be available through the ‘Cloud’. Would Atrenta allow its EDA tools to be available over the ‘Cloud’ for usage by other companies?
A. We have started to use the cloud for our tools. But adoption of the cloud as a delivery or access vehicle for EDA tools is still at a very early stage. We have signed up with some cloud-based providers and as this trend picks up we will surely support it. There is nothing unique or special about supporting tools through the cloud. It is more of a business model than anything else.

Q. What would be the main take away of using the Cloud-based business for EDA tools?
A. Probably the number one reason would be to make the tools available at a lower price point but in a very limited way so that it is available more easily as well. Every time one would use it, you would have to pay a small fee. Apart from this, the cloud providers allow you to manage your IT, particularly in an overload situation. There are big server farms that are running these tools overnight so when smaller companies come to a tape out phase, they can use the Cloud for extra compute capacity. The cloud for EDA and the chip business is still young because people are concerned about the security of their designs. Running the tools either on a server or on a laptop or in the cloud should not make any difference. The results can be accessed graphically through the Intranet. The biggest issue is the protection of the designs and the tools.

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Q. So being with EDA, even when it was not born commercially, what was the trend that you have noticed? Was there something in the 80s that has then been pushed down and new design trends that have been enabled later?
A. The basic driving forces of EDA right from the beginning of time have remained almost the same. There are complexities, new physical effects as you go to every technology node and commercial forces such as time to market. Previously, all chip design was done inside of one building and now this process is distributed all over the world. Then there came the commercial pressures of time to market as consumers became more dominant forces.

Q. Since EDA tools are expensive, what are your thoughts about approaching the smaller, independent design companies like in Bangalore?
A. From a global point of view, we do support many early stage companies although I do not have a number of how many small companies we support in Bangalore. Globally speaking we support lots of start ups all over the world. This is because we have a big impact on cutting down design time. There are many small companies that are using ARM-based processors and graphics processors that require our software to meet their time to market demands.

Q. Does Sri Lanka look very promising in the design sector for Electronics?
A. There is a trend to go into countries where the education system, particularly in science and math, is strong. You then make your investment in training people in software or chip design or EDA tools. It’s not at all a unique thing for us. The uniqueness is that we are doing it in Sri Lanka, although people have been doing this in many other countries like Vietnam, Romania, Egypt, etc. We found Sri Lanka attractive because of its strong engineering population and proximity to India.

 

About Atrenta

Atrenta has been in business for about 12 years and many of the top chip companies are our customers. We are the largest private EDA company. We are present in 11 countries, amongst which we have 5 R&D centres. Our headquarters are in San Jose, California, though India has been our largest R&D centre from the very beginning of the company. We have at least 65-70% of our team dedicated to R&D, so we are a very technology focused, technology rich company.

Dr. Ajoy Bose’s connection with EDA
I have been in EDA all my life right from when I was doing my PHD in the 70s. I had a desire to create an EDA product that would have a major impact on the way designs were done and on the EDA technologies that are available. I was associated with Verilog. The original Verilog development team used to work for me so I feel very good about the fact that I am going to be associated with two industry leading names- Verilog and now SpyGlass. So what motivated me was a passion for EDA, my background in EDA and a desire to do something that would have a lasting impact on the industry, on the way designs are done and on EDA.


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