Selecting the right process node impacts the power, performance, time-to-market and unit costs incurred for the final product. This interview takes a look at what questions design engineers should ask themselves, before selecting the right process node.
Sunit Rikhi, vice president of the technology and manufacturing group and general manager of Intel Custom Foundry, Intel Corporation, speaks with Dilin Anand of EFY.
Q: Could you give us an idea of what a design engineer needs to figure outin order to capture the design onto the right node?
A: First of all, you have to select the node before you design and not after you design. Maybe the front-end of the design needs to be defined earlier, but you still need to know what kind of transistors you need (or have) to play with in order to make the design work according to the intended specification of the product. You need to have the selection of the technology done way up front, and that is the most important thing.
Q: I’ve heard that the leading edge is good for digital and not good for analogue. Is this true?
A: I think this is over simplification. Simplification and abstraction is necessary, otherwise we will perpetually be looking for the “devil in the details”. So you have to come up with some simplified conclusions like“the leading edge is good for digital and not good for analogue”. The interesting thing is that it is not wrong, but it is not right either – because the devil is actually in the details.Gordon Moore in his original paper said that the impact of integration on linear circuits (he called analogue as linear) is not going to be as dramatic as digital – this was back in 1965. He goes on to say that, however, we will see significant integration of linear circuits in the future.
Q: What would be your advice to engineers faced with this question?
A: My advice would be to let the product level targets drive the decision. If the overall product needs the power, performance and cost targets that can only be achieved through an integrated digital & analogue circuity at an advanced node, then that node should be the target. We’ve been putting analogue circuits on advanced nodes because that is where the economics is. For instance,there are analogue functional blocks called Serialisers and Deserialisers or SerDes. Today, on an Intel 14nm technology (there is nothing more leading edge than that) my foundry group has a 32 gigabits per second SerDes implemented and silicon proven. These are being integrated in large systems on chips made on our 14nm silicon technologies.
If all you are doing is stand-alone analogue processing, and the chip is largely analogue, it is very possible that there is not enough hunger in such a product for leading edge digital high-speed switching transistors.
Q: What is the trade-off here, is it the cost of the wafer?
A: The cost of a wafer is not the key thing affecting this decision. It is the cost of the transistor that you are using. In most cases, the cost of a transistor is far cheaper in leading edge (despite a higher cost of wafer) than on the trailing edge, and that’s when you make a decision to go for the leading edge.
Another thing that needs to be considered is the increasing development costs including mask costs at the leading edge. To minimize the burden of these amortized development costs on product costs, there needs to be sufficient product volume. For low volume products, trailing nodes are going to be much easier and cheaper given the availability of libraries and IP, as well as beneficial mask pricing compared to a leading edge node.
Q: Apart from transistor costs, what else affects the economics here?
A: There is also this question of when your product lands in the technology cycle. At the very front end of a new technology node cycle, wafers are very expensive and there is no well-developed portfolio of IP blocks available from the foundry or the eco-system. Products that are designed to intercept this very front end of the cycle bear the burden of developing the needed IP and the higher cost of wafers. Products that intercept the technology cycle later benefit from a more mature portfolio of IP blocks and a reduced cost of wafers based on technology learning and depreciation roll-off.