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The intellectual property (IP) can be in many different shapes and forms: software, hardware, on-chip, on-board, soft IP, hard IP, design IP, verification IP, etc. Assuming that we are talking of silicon IP, the designs have only become more complex with a lot of different interfaces being integrated onto the same piece of silicon.

According to Giles Peckham, EMEA marketing director, today’s advanced 28nm design processes enable FPGA companies to put up to one million logic cells onto a single piece of silicon.

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“Creating designs of hundreds of thousands of logic cells, especially when performance requirements are high, requires the use of IP from the FPGA vendor, third parties and typically reuse of previously designed modules. Electronic system level (ESL) synthesis tools can help maintain high levels of productivity but these are used today to create additional high-level IP blocks,” he says.

Anil Gupta, managing director, Applied Micro Circuits India, says, “The advanced technology nodes allow greater integration and this further creates an opportunity to put more varied interfaces on the same chip. Given the enormity of globally distributed teams working on these chips and the complexities involved in simply designing and implementing the core portions, there is an acute awareness and push to identify reliable suppliers of various IP blocks, especially those which are considered standard fare or those which require specialised skills like analogue or mixed-signal. These include the typical memory interfaces like DDRx, peripheral interfaces like USB, SDIO/eMMC, analogue IP like the data converters, etc.”

For early designs at a particular technology node, the challenge remains that the IP is often developed and verified at the same time as the chip development. Often the manufacturing process technology is also evolving at the same time, complicating this even further. This adds significant risk to the schedules, as the IP may not be production-ready by the time the chip needs to tape-out. IPs for advanced nodes often take a couple of rounds of silicon to end up bug-free.

Irrespective of the risks involved, design teams today have little choice but to go to IP developers to get whatever IP they can. That is the only way to meet the tight schedules and time-lines (thus improving design productivity), according to Gupta.

Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems in India, adds, “Over the last few years, the rapid growth in the consumption of electronic gadgets such as wireless handsets, tablets, gaming devices, 3G-/WiMax-enabled netbooks, set-top boxes and smart cards has increased design complexity. At the same time, semiconductor companies are under constant time-to-market pressures to bring out newer designs more quickly and at lower costs.”

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Increasingly, IP is becoming an option for companies to address the issues of complexity, time-to-market and profitability. As per the data from ChipEstimate.com, Cadence’s chip planning solutions business unit, the IP portion has grown from around 40 per cent in 2004 to 70-80 per cent today in ASICs and ASSPs. This is based on well over 100,000 chip estimations, so the data is quite extensive.

This leads us to the question of expense management and how it’s driving the growth of third-party IP vendors.

Expense management
Peckham notes that the demand for third-party IP has been created more by the need to achieve productivity levels that enable FPGA designers to quickly get their products into emerging markets rather than the need to reduce design costs.

He adds, “For third-party IP vendors to thrive, they also need to deliver their IP in a package of representations that conform to industry standards and are compatible with multiple FPGA product families.”

Ahuja says, “While the use of commercial and in-house IP can reduce the overall cost of the design, integration is a challenge and there has been an increase in the cost to integrate various IP blocks into a complex SoC architecture. These costs continue to rise with each new generation of SoC largely driven by the dramatic increase in the number of IP blocks infused into the architecture.”

Another aspect to cost and profitability is the amount of effort made by the silicon designers to create the advanced SoC architectures expected by end-users for each new generation of silicon.

The IP ecosystem needs to change so that SoC design can adopt a system-level-driven approach to resolve issues like those mentioned above. The IP must be designed from a system-level point of view from the very beginning in order to make it easier for the silicon architect to adopt and use in his design. At the same time, the IP must allow for ease of integration into the design.

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According to Gupta, for design teams driving early adoption of new technology nodes, expense management does not directly play a role in the decision to go for an IP from a third-party vendor. It is typically the nature of the IP, the limited resources inside, the tight timelines of projects, and the expertise and history of the IP vendor that drive the decision.

However, once the IP on a particular technology node has been tried and tested and the process technology node has become mainstream, expense management in terms of development resources required, the costs involved and the schedules involved start to play a huge role. The major challenge is not necessarily the design of the IP but rather the verification and validation of the IP to ensure that it works perfectly fine to the desired specifications.

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Thus the value of an IP that has been used a few times by other customers is very high. It gives the design team the confidence required not only in the IP itself but also in the fact that others have successfully integrated that IP into their own design environments to develop their chips. It dramatically lowers the risks involved and becomes a no-brainer on expense reduction compared to in-house development.

Key players outsourcing IP
One other aspect to note is that the key players are now able to increasingly outsource IP.

According to Peckham, the adoption of industry standards as already mentioned together with a tool suite such as Vivado Design Suite from Xilinx—which supports multiple languages such as VHDL, Verilog and System-Verilog in the HDL domain, C, C++, System C and Simulink model-based design in the ESL domain—are all developments that have facilitated increasing levels of outsourcing.

According to Ahuja, an important trend is that large semiconductor companies which would have previously rarely considered purchasing external IP except for perhaps an ARM core, are now changing their strategy and beginning to embrace external IP. One of the key enablers of this trend is the protocol IP space, as this removes the need to invest internally and creates a piece of IP that is designed to meet a particular specification. Instead, buying it off-the-shelf can help to verify its quality more quickly.

Gupta notes that working with a third-party outsourcing partner to procure an IP has its own challenges. The design methodologies followed by the customer vs the IP vendor matters a lot. Once the customer has become used to working with a particular vendor on one or two IPs, and the vendor also has had the experience of working with the customer, it becomes a lot easier to work together. Both parties understand what to expect and the methodologies are aligned to ensure that there are few unknowns that kill the design at a later stage.

“Success breeds success. Thus a successful relationship between the customer and the IP vendor on one or two IPs will invariably lead to a longterm collaboration,” he adds.

Changing landscape
How is the growing trend of third-party IP vendors and an increase in the licensing of advanced IP blocks by several key players likely to change the landscape of the global semiconductor IP market?

As per Gupta, it is fundamentally a business need that is driving the whole IP ecosystem consisting of the vendors and their key customers. With the increase in complexities of design and new product introduction times continuing to shrink, the need for reliable, working IP from trusted vendors will always exist and only grow.

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“In fact, history has shown that IP vendors that have proven their mettle typically end up being acquisition targets of one of their larger customers if the customer realises that he would require significant IP from the vendor and there is a unique or special expertise that exists in the vendor team. In fact, EDA companies have also eyed the IP market to acquire strong IP vendor companies as they recognise strong synergies with them. The IP complements and strengthens the tool and methodology offerings from these EDA companies.”

Thus standardisation of design interfaces and key technology expertise will continue to drive the creation of IP vendor companies. The challenge for them would be to have strong financial backing and the ability to sustain for long periods since success in the IP business takes time. The risks of an IP business are similar to the risks of a product company, except that the IP company requires lesser capital upfront than a product company. And the success of an IP company takes much longer to realise than of a product company which either succeeds or fails quickly.

Xilinx’s Peckham adds, “The market for hard IP in ASICs, ASSPs and PGAs will continue to grow as device complexities increase. But the market for soft IP in FPGAs has now been given a high growth path through the introduction of tool suites such as Vivado with its novel IP packager and IP integrator tools and the development of IEEE1735 for design security.”

What’s ahead?
AMCC’s Gupta foresees more IPs, more IP companies and more IP usage. Peckham at Xilinx notes that the increasing design complexity will demand higher levels of design abstraction with the use of both high-level synthesis and IP in its various forms. “Future process nodes will be challenged to deliver such rapid cost benefits as we have seen in the past. So there is likely to be an increasing pressure on IP developers to either reduce the silicon area or the number of logic cells required to implement the required function,” he adds.

For a long time, there has been a practice of recreating the core components rather than using readily available designs. The main reason for this is the lack of trust due to absence of standard designs. With increased pressures of reducing costs and time-to-market, we will definitely see a trend towards building IP and using third-party IP in order to avoid re-inventing the wheel every single time,” concludes Ahuja.


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