The ‘chips’ are everywhere today, right from mobile phones and computers to microwave ovens and washing machines, and even in children’s toys. There are millions of chips in the world and more are being produced every day, but did you know that these are still produced by a countable number of manufacturers across the world? A fab, or a semiconductor manufacturing plant, is a technology- and resource-intensive factory that could cost anywhere between 1 billion and 10 billion dollars, or even more to set up.
The challenges and resulting improvements in semiconductor fabrication technology can be attributed to the complexity and sensitivity of the whole process. It could take six to eight weeks per batch right from wafer processing and die preparation to integrated circuit packaging and testing. What’s more, it is a very sensitive process too. As chips get smaller, purer materials are sought. The ‘clean rooms’ of fabs, where most of the processes happen, need to be cleaner than you can imagine. Human workers need to wear special suits so that chips do not get contaminated. High-precision machines are needed because working is required at the micrometre and nanometre scale with very sensitive materials.
As the industry transitioned from micro- to nanometre scales, the onus was on the fabs to execute the engineer’s dreams, and they did. Now even 40nm and 30nm technologies have entered the mainstream and smaller feature sizes are on the anvil. Technologies such as three-dimensional integrated circuits (3D ICs) are promis-ing a dramatic reduction in the size of chips in this decade, while research in the field of carbon nanotubes is indicating the arrival of a revolution as innovations continue to fire our dreams.
However, Pankaj Sathe, executive director and head of the Semiconductor Solutions Group, KPIT Cummins, provides a very practical perspective. He says, “The trend towards lower geometries and faster transistors has somewhat slowed down. In an effort to keep pace, parallel computing is evolving. It is expected that even embedded devices will have more than 60 microprocessor cores by 2015. And, since speed is no longer the main differentiator, improvement in manufacturing technologies are no longer sought after so much, as in the past. However, yield improvement technologies are gaining traction in the physical design space.”
This is not to be misconstrued as a reduction in the amount of innovation in the space. It is just that the goals are changing. Today, researchers are working to address immediate concerns such as yield improvement, power management, cost and time-to-market, while also looking at futuristic options such as carbon nanotubes.
There have been significant developments in recent times. Listing some examples, Professor Srikanth Jadcherla, chairman and CEO, Seer Akademi, says, “Kingston has developed what it claims to be the fastest Intel-certified memory in the world, which runs at 2400 MHz. Samsung has announced that it is now shipping 32GB NAND memory chips using 30nm technology, allowing to double the capacity of Samsung’s previous generation. 45.72cm (18-inch) wafer prototypes are being talked about.”
Sathe adds more examples such as the mainstream adoption of 40nm manufacturing technology that is helping some semiconductor sectors improve manufacturing margins and the adoption of the fab-lite model that is helping in removing manufacturing volatility.
Let us take a look at some of these developments.
Chips in 3d
3D IC technology appears to be a greatly discussed development in the semiconductor fabrication world. In a 3D IC, two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. There are many types of 3D ICs and many techniques for making them. One futuristic option is a completely monolithic 3D chip that is fabricated on a single semiconductor wafer. As of now, the 3D options include wafer-on-wafer, die-on-wafer or die-on-die layering with some form of interconnection.
Flipped chips. Few basic forms of layering have been done for some time now—here, one chip is flipped on top of another and attached at specific bonding areas where micro-bumps are grown to create die-die interconnects. Digital camera chips often use this technology to attach the charge-coupled-device image sensor to the image-processing chip. The technique can also be used to put a memory chip on top of a logic chip, as in the case of Apple’s A4 chip. Industry-wide initiatives are on to standardise the pattern of micro-bumps to use for flipping dynamic random-access memory (DRAM) units atop processor chips. However, this type of flipping actually involves two separate chips, and cannot really be considered a 3D IC.
Through-silicon vias. The most prominent technique for making true 3D chips today is by using through-silicon vias (TSVs). TSVs are vertical interconnects that link the many layers in a 3D IC. A TSV connects the two opposite sides of a silicon die or wafer. It runs from the front side of a wafer, typically connecting to one of the lower metal layers, all through the wafer and then out through the back.
TSVs are extremely thin and fragile and pose several challenges during fabrication. First, since the via goes through the active area and some of the metal layers, a large area around the TSV must be left free to avoid damages to the layers already deposited. Second, while manufacturing such chips, there is a risk of altering the threshold values of nearby transistors due to the stress applied to the silicon substrate. This could, in turn, alter the performance of the chip in unpredictable ways. Despite the challenges involved, TSVs are considered as the main option for the design and manufacture of 3D ICs.
2.5D. Semiconductor manufacturers such as Samsung and Xilinx have started using TSV technology in some of their chips, but the industry calls this slightly simpler version of 3D TSV usage as 2.5D. It is important here to define both 2.5D and 3D IC technologies. In 2.5D, one or several dies are mounted to another ‘inactive’ die with TSVs in order to route nets between the active die and the substrate. This technique involves the use of inter-posers, or electrical interface routing between two sockets or connections, to spread a connection to a wider pitch or to reroute a connection. A full 3D IC can be seen as one or several dies mounted to the backside of an ‘active’ silicon die through TSVs.
Xilinx, for example, uses a 2.5D technology called ‘stacked silicon interconnect’ in its new range of Virtex-7 field-programmable gate arrays (FPGAs). This method involves creating small dies and then putting several of them on a silicon interposer, instead of opting for huge dies which would not yield economic volumes. The Xilinx interposer consists of four layers of 65-micrometre metal on a silicon substrate. TSVs through the interposer allow this metal to be connected to the package substrate. Micro-bumps allow four FPGA dies to be flipped and connected to the interposer. The use of an interposer makes power distribution across the whole die simpler, and is believed to be the only 3D IC technology in high-volume production today.
While this technology may be applied to memories, FPGAs, micro-electromechanical devices and CMOS image sensors, experts feel it is not yet ready for application-specific integrated circuit applications. Once more design tools are available and the manufacturing and thermal management challenges in the use of TSVs overcome, we can expect to see full-3D ICs playing a huge role in the era of 20nm or smaller chips.
One must understand that 3D IC technology is not merely a stacking of components using vias instead of wires—if it was, it would go nowhere. Like the multi-core revolution, it requires new architectures and software.
The 3D IC technology has been talked about for the past eight years, but suddenly seems to be gaining momentum since last year. Global Foundries and Qualcomm announced a collaboration to work on 3D ICs in March 2010. Taiwan Semiconductor Manufacturing Company launched work on 3D IC design using interposer technologies in June. UMC, Pericom and Elpida made collaborative announcements concerning the development of DRAM/logic stacks. In September, Nokia declared that it would introduce a wide input/output (I/O) 3D inter-face in 2013. Xilinx launched Virtex-7 in October. Micron has suggested that it might be launching its hypercube in 12 to 18 months and Samsung is going big on wide I/O memory. In short, there is a lot of activity in TSV-based 3D IC technology space, and we hope to see some significant progress in the next two to three years.
Efforts to improve yield
In the process of semiconductor fabrication, the proportion of devices on a wafer found to perform properly is referred to as the yield. Due to the complexity and sensitivity of the process and the components, there are many factors that reduce the yield of a semi-conductor fabrication process: Particle contamination, micro-scratching, wafer breakage, wafer misalignment, robot malfunctioning and even tool vibration due to environmental forces such as air flow. While these are general problems that have been haunting semiconductor fabs for years, newer yield-related problems have come about due to the reduced geometries. New techniques are emerging to conquer these problems.
New challenges. At 32 nm and below, the intricate process and layout interactions cause failures that are not foreseen by normal simulation tools. Irregularity in logic also causes failures. The very low ‘k’ factors in lithography are also causing problems these days. At the 32, 28 and 22nm levels, this leads to design sensitivies such as hot spots (areas on the die surface that exhibit excessive heating).
Modelling and simulation. Everything including system-level power, gate oxides, etch transfers and line edge roughness has to be measured, modelled and simulated—nowadays even at the atomic level—to spot such problems. Some fabs monitor as many as 50,000 points. Of course, errors do not show up immediately by watching a single wafer. Sometimes, they are found only after monitoring hundreds or thousands of wafers.
From fab to design and back. The key goal behind such modelling and monitoring is to immediately identify problems and their root cause, and correct them at the design stage. All metrology data from the fab has to be fed back to the design centres, and design improvements flown back. This is what most latest diagnostic tools such as those from Mentor Graphics and Synopsys attempt to do. From lithography, manufacturing process to object-oriented process control, everything has to be taken care of at the design stage. This is leading to adoption of many techniques like design-based inspection and design-for-manufacturing (DFM).
“DFM is one area where improvements are being made specifically in phase-shift-mask and OLE process control (OPC) techniques. However, exactly how they help in improving the yield is not clear,” says Prof. Jadcherla.
Identifying problems and improving the yield is no mean task and could take around a year to achieve even for the most experienced companies—as it happened during the introduction of the 40nm process at TSMC, the world’s largest semiconductor manufacturer. When a new manufacturing process is introduced, it is first developed and refined in a test fab and then transferred to production lines in a process called ‘chamber matching.’ This theoretically ensures standard conformity and higher yields. Problems with chamber matching on TSMC’s 40nm lines caused yield problems, thereby making it difficult for the company to match up to the demand for 40nm technology. It took almost a year for them to iron out these problems and plump up the yield of the process to match the previous generation’s.
Improvements in lithography
Lithography is one area in which a lot of improvements have been made, and are expected in the near future—especially due to the advancements made in photonics. As chips become smaller, there is an imminent move from 193 to 13.5nm-wavelength lithography in order to pattern finer features. This is due to a new lithography technology called ‘extreme-ultraviolet’ (EUV) (http://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography) which could allow current chip features to shrink by almost ten times. Since 2009, a variety of EUV tools have been launched, including EUV scanners for process development and EUV light sources.
Apparently, EUV requires a completely new yet cost-effective and reliable light source. Versions have been demonstrated that hit 100W output power, enough for minimal production. However, high-volume manufacturing will require double that figure. A recently launched EUV source from Cymer Inc. of San Diego uses a high-powered infrared laser to bombard a microscopic molten tin droplet as much as 50,000 times per second. The resulting plasma radiates photons over a range of wavelengths. The 13.5nm light is collected and directed into the scanner illuminator. Japanese company Gigaphoton Inc. is also pursuing a similar laser-based approach. The company has announced plans to start shipping EUV light sources this year.
It is expected that by 2012, production systems for volume manufacturing using EUV lithography will be available. However, this is assuming that certain hurdles are mounted. Making masks of sufficiently high quality, for instance, is still a challenge. Another is checking for defects in those masks initially and after use. Companies such as KLA-Tencor Corporation and Carl Zeiss SMT are making mask inspection tools capable of handling 22nm logic node EUV masks. However, these work using 193nm sources, and it is believed that they will work only up to 16nm process technology. So, what after that?
A review of the recently held SPIE Advanced Lithography – EUVL Conference by Vivek Bakshi (http://semimd.com/blog/2011/03/07/2011-spieadvanced-lithography-%E2%80%93-euvl-conference-review/) provides an excellent overview of recent methods in lithography and metrology.
Experiments with newer materials
Silicon has dominated the semiconductor manufacturing space for ages and, frankly, it is still one of the best materi-als for chips. However, new materials are being experimented for newer applications and smaller geometries, but none has moved beyond research to volume production yet. As long as we continue with the same material, improvements will only be incremental.
Electronic devices such as touch-screens, flexible displays, printable electronics, solidstate lighting and thin-film photovoltaics, for example, would be much better off with flexible transparent conductors. Standard indium-tin xide films are unlikely to satisfy future needs due to losses in conductivity on bending and the escalating cost of indium which is in limited supply.
“Recent research related to graphene indicates that it may be suitable as a transparent conductor. Graphene hybrids with carbon nanotubes, for example, may prove to be especially interesting,” explains Prof. Jadcherla.
Some companies have also been experimenting with polymer-based semiconductor manufacturing. Other materials like bismuth telluride and molybdenite have also been checked up. However, carbon nanotubes show much more promise than any other option, although not in the short-term. A lot of disparate but promising research is happening on that front. Last year, IBM revealed carbon nanotube air filters for semiconductor manufacturing. In January, TSMC patented a carbon nanotube bond pad structure and the methods for using it. In February, Prof. Yutaka Ohno from Nagoya University in Japan and Prof. Esko Kauppinen from Aalto University in Finland shared details of a simple and fast process to manufacture high-quality carbon nanotube-based thin-film transistors on a plastic substrate. This can go a long way in producing cheap, powerful electronics. However, it might be years before carbon nanotubes really come into semiconductor manufacturing in a big way.
“Nanotubes and other materials are not yet on the horizon as far as volume manufacturing is concerned. This trend is unlikely to reverse in the next 5-10 years. But yes, a revolution is expected. Carbon nanotubes are expected to become mainstream in a decade,” says Sathe.
There are lot more trends catching up in the space. For example, device makers are moving towards a fab-lite model, whereby they handle only the designing and outsource the manufacturing to foundries, in order to avoid the cost of setting up a fab and the problems caused by changes in technology and demand.
Another trend is the focus on reducing the time-to-market. Since not much can be done to reduce the actual time of manufacture, the onus has shifted to the design stage—more capable tools and processes are helping to reduce the time taken at this stage.
Sathe agrees, “The time taken for manufacturing and post-manufacturing process is generally fixed. Hence the emphasis is on reducing the design cycle time. An approach preferred these days in creating bigger system-on-chips is to reuse or buy intellectual property, and to work with design partners rather than in-house development. The integrated device manufacturers are looking at a faster time-to-market and increasing market share rather than a complete in-house design approach. New methodologies brought in by electronic design automation vendors, e.g., Magma’s methodology to accelerate analogue porting and optimisation, also help in this.”
There is also an attempt to move from the current 30.5cm (12-inch) wafers to 45.7cm wafers. The 30.5cm, 300mm wafer-based technology, which itself is kind of new, yields 2.25 times more chips per wafer than the older 20.3cm (8-inch), 200mm wafers, yet they take just about the same time to pass through a factory, reducing the cost per chip and significantly boosting total monthly output. A 45.7cm wafer plant would show a similar reduction in per-chip cost and increase in output. However, as of now, nobody can afford a 45.7cm fab. An industry conglomeration, including TSMC, is looking at how to make 45.7cm fabrication more affordable. The company expects to bring it into operation by 2015. Let us wait and see what other changes happen by then.
The author is a technically-qualified freelance writer, editor and hands-on mom based in Singapore