Modern electronic warfare (EW) system developers are facing multiple challenges including increased spectral congestion and surveillance of wider bandwidths at a greater level of detection sensitivity. In addition, the push on system developers to reduce development times strains many of the existing development models, resulting in custom hardware and firmware designs to achieve improved levels of performance within size, weight, and power constraints. New giga sample per second (GSPS) high speed converters, high performance field programmable gate arrays (FPGAs), and FPGA intellectual property (IP) cores are now changing the status quo, providing designers with off-the-shelf solutions and configurable building blocks to meet the next generation of challenges. A reference design, featuring GSPS analogue-to-digital converters (ADCs) with FPGAs and channelisation IP, will show how designers can achieve faster time to market with state-of-the-art solutions for electronic intelligence and digital RF memory systems.
EW systems identify and counter electronic threats such as surveillance and tracking radars. EW systems are commonly categorised as either electronic support (ES), electronic attack (EA), or electronic protect (EP). ES systems intercept and measure signal parameters to identify the signal’s sources and perform threat analysis. The EA systems generate jamming signals to overpower the true pulse. Digital radio frequency memory (DRFM) is a spoofing technique to deceive radars. The EP systems concentrate on processing and storing the incoming signals to construct a signal database. This database is a continuously updated lookup table used to identify future radar systems. Traditionally, these systems were developed on an analogue platform. Modern systems are significantly more digital to take advantage of the signal processing capabilities available in the programmable logic devices. Threat detection from unknown targets in these systems requires a receiver, which can operate over a wide frequency band to identify and initiate countermeasures to the threats. Typical EW systems may operate over a range from DC to 20GHz. Beyond wide bandwidth requirements, practical EW systems require high dynamic range, high sensitivity, and accurate pulse characterisation as new systems are being pushed to examine the bandwidths of interest faster with greater levels of detection sensitivity. More complicated situations arise when incoming signals to the EW system may be from numerous sources, each of which needs to be identified and distinguished. Independent of intentional interference from adversaries, increased spectral congestion, particularly from the rapid expansion of communications infrastructure, has made effective detection even more challenging. Complex systems with even lower size, weight, and power targets are driving longer development cycles. However, next-generation, off-the-shelf solutions coupled with programmable building blocks provide solutions to these challenges. Two of the key building blocks critical for any EW system, the analogue-to-digital converter and real-time channelisation IP, will be examined further to illustrate how these challenges are being addressed.
ADC Bottleneck in EW Systems
In many instances, the high speed ADC transition from the analogue to the digital domain is the limiting factor in ES, EA, and EP systems, where the system architect is often faced with a conundrum. While minimising cost and system size are usually the top priority, the system designer must also strike an optimal balance between the need to increase instantaneous surveillance bandwidth to maximise the probability of interception, and how to minimise the effects of in-band, high power signals that desensitise the system. These requirements pose challenges in the converter design and the front-end design that couples the signal content to the converter. Even if the converter itself has excellent performance, the front end must be capable of preserving the signal quality, which results in the relentless push for performance and cost on the limits of high speed ADCs. Figure 1 illustrates a simple EW system. The key features of the system are an RF receiver, used to down-convert and select the band of interest for interrogation, the ADCs used to transition the data from the analogue-to-digital domain and the digital signal processing engine, which is typically an FPGA configured to detect, determine, analyse, and manage the storage of signals of interest. DRFM and EA systems also include a corresponding transmit chain utilising a high speed digital-to-analogue converter (DAC).