Considering that every chip in the world and every transistor on the chip are tested, just imagine the amount of time and cost involved in testing millions of chips with billions of gates. semiconductor manufacturers are always looking for ways to reduce the test time and cost
SHWETA DHADIWAL BAID
Even if you use all the latest tools for your pre-silicon verification and develop the most accurate model near to the actual system, the biggest challenge is to get the first working silicon,” claims Rajamohan Varambally, director-technology R&D, STMicroelectronics, India.
The primary goal of post-silicon testing or validation is to ensure that the intent of your design is met. Varambally adds, “Making a chip for the first time will cost several million dollars. This is why whatever can be done with software is done beforehand so that the chances of coming up with correct silicon first time itself are high. However, software cannot simulate the entire working. Final testing has to be done on silicon.”
Silicon design and manufacturing processes have evolved over the years. Neeraj Rai, verification signoff manager, ASIC division, eInfochip, says, “The industry is dynamic and the methodology and languages have changed. The level of abstraction is a lot higher today. To support this, tool vendors and test equipment providers have developed more efficient and automated test systems.”
Post-silicon validation or testing has two aspects. Naresh Kumar, general manager, applications (EMG), Agilent Technologies, explains, “Once the first silicon is made, it is tested for functionality using discrete equipment or configured automated test equipment (ATE) before sending for mass production. Every chip produced is then tested using large testers.” In functional test, fault-finding or debugging is critical, while in production time-to-test is critical.
SoC: Need for embedded multi-functional tester
As every chip is designed for different purpose, the test parameters and process for functional test vary from chip to chip. Testing a chip for its functionality is basically providing a stimulus and measuring the response. There are advanced test systems like the ATEs which are configured to perform test on a particular chip.
“Once the designer provides specifications of the integrated circuit (IC), test programs are written to test its functionality. The program will feed in the inputs and measure the corresponding output to validate the functionality as per the specifications,” explains Veerappan V., co-founder and president-operations, Tessolve.
Rai adds “A test program written to test an analogue-to-digital converter (ADC) will be much different from the test program written for testing MP3 decoder chip.” It is very important to correctly program the ATE to do the functional testing.
There are analogue, digital and mixed test systems to test various parameters of the chips. The development of system-on-a-chip (SoC) demands testing of multiple functions simultaneously. The biggest challenge here is the development of multifunctional test programs. Embedded multifunctional test is of increasing importance in enabling SoC technology. There are software tools that help in test program conversion and enable smooth multifunctional tests.
Characterisation and reliability tests
Apart from testing for the actual functionality, the chips need to be tested in several different environments. Chips are tested for various domains like electrical validation, thermal characterisation, voltage and current graphs.
Electrical design validation helps to assess whether the given IC complies with a variety of different operating specifications, while reliability analysis helps to deduce the long-term reliability of the semiconductor and its suitability for intended applications.
Veerappan explains, “If a chip has a certain operating temperature, its performance is tested for varying temperature. Similarly, if the chip operates at 2 GHz, its operation is tested at 1.9 GHz and 2.1 GHz.” It’s like quality certification of the finished device before it goes for mass packaging.
Kumar says, “In addition to functional testing, DC and AC parametric testing is a big challenge, as with new processes the transistors need to be characterised and verified for their DC and AC characteristics. There are parametric tests which are performed to understand the semiconductor reliability, lifetime, device breakdown limits, etc. Typically, they involve current-voltage and capacitance-voltage characterisation of devices and then deriving reliability and other parameters from these tests.”
Biggest claim: chip is not working
The first working chip itself is a big challenge. Varambally says, “Another big challenge is to conclude that chip is faulty. One person cannot comment on that. So you need a team of experts to conclude that the chip is faulty or the design is faulty.”
Detecting a bug is not the only key thing in testing, pinpointing it in a large and complicated chip is also very important. “Several years ago, designing and testing were two independent processes. Today, a new process of concurrent or co-design and verification is used where the designer and test engineer work together to detect the fault at an early stage,” shares Neeraj Bhardwaj, systems hardware architect, Texas Instruments.
• Logic analysers
• Pulse pattern generators
• Arbitrary waveform generators
• Semiconductor parametric analysers
• EDA tools
• Design-for-testability tools
If the chip fails, a series of tests are performed to locate the fault. This is done by the chip designer himself. Veerappan says, “Sometimes we cut open the chip to find the problem and inform the designer where the design went wrong.”
Logical tests help in detecting where the input and output mismatch. “These digital test results help to find the point of failure and do detailed analysis,” explains Varambally. He adds that checking the nodes of abnormal current and voltage, waveform shapes and signals and comparing them with the expected values helps in debugging.
Even standard test equipment like logic analysers and pattern generators have evolved over the years to help ensure that there is a smooth handover from design simulation to actual device test. Kumar explains, “This is achieved by providing linkage for accepting test vector inputs from design tools. Designers can create test vectors in VHDL, etc, and the same can be imported into pattern generators to actually generate and apply the same to the ICs as digital stimulus.”
Design for testability
You must be able to test every design to ensure the intent of the design. “If the design is not testable, it may be very difficult to find the fault after packaging. This involves cost and time,” explains Veerappan. There are different software tools available from companies like Cadence and Synopsys to design for testability.
Varambally explains, “Let’s say there are millions of transistors, but only hundreds of pins. Practically, you should be able to test any chip failing through only these pins. The concept of design for testability applies to testing of all the transistors or different sections of the chip.” There are different test nodes created to test various sections of the IC.
Advanced test equipment are very expensive. So the time involved in testing each chip is very critical. “Design for test helps reduce the time to test one chip, thereby increasing the utilisation factor of the tester. So you need to design the chip such that your testing time comes down,” explains Varambally.
The cost of a chip design is millions of dollars, which also includes the cost of test. To minimise the cost and perform the test efficiently, sometimes an extra circuit is added to perform tests.
Varambally says, “We inculcate all the testing features in the design stage itself. For example, we can put a small extra structure along with the circuit, like a small block. Although there is a small price associated with this extra piece of silicon, it will reduce the testing time and cost. So it is okay to pay a bit of silicon fully for testing.”
Embedded selftest inside the chip itself is a logical and viable future solution for complex SoC designs that saves test development cost and reduces the load board and ATE system complexity.
Sabapathi S.R., chief executive officer, Qmax, says, “The built-in selftest can be commanded by simple low-cost JTAG interface. This will cover the functionality of the device. Henceforth ATE test will be much simpler and in some cases limited to DC and AC parametric tests alone. The resultant savings easily justify additional silicon block embedded into the chip.”
After the silicon has passed the tests and the chip is sent for mass production, every chip produced undergoes similar tests. Every chip is tested for its functionality and characterisation. Testers are preloaded with test programs to test the ICs. There are tools for signal integrity and thermal management tests.
A go-no-go test is performed on every chip in big test assemblies called ATEs or testers. Veerapan explains, “There are test load boards to load the chip into the tester. The test program is customised. Every pin of the IC has to be activated by some signal, and the tester will send the signal and receive an output, which will then be compared with the expected output. So, basically, the tester simulates the test as if the end customer is using the chip.”
Designing of test load boards is another critical area requiring skilled test engineers. Varambally adds, “Another key consideration is that one tester can test only one IC or range of ICs of a particular category. There is no universal tester that can be used to test all the ICs in the world.”
For better and faster testing
The design and test methodology has to evolve with the increasing complexity of silicon design. “Testing is becoming an integral part of design. Unless you have very good test methodology built into your design tool and at design stage, it will lead to critical problems. So designers and test engineers have to work hand-in-hand. Unless these guys work together, testability will become a problem later,” claims Bhardwaj.
Concurrent testing is an effective method to drive the test times. This can be accomplished by testing different cells of the same silicon in parallel, i.e., testing multiple cells at the same time wherever possible. As the SoC is a combination of various digital cores like ADCs, DACs and digital and analogue cells, all of these can be tested in parallel and then the entire device tested for functionality. This will reduce the overall time significantly.
“Another test strategy offered by ATE manufacturers is parallel multi-site testing where multiple devices can be tested simultaneously (at more than 128 sites), reducing the overall test time and increasing throughput significantly,” comments V.K Rajiv, product manager, Qmax.
Many semiconductor manufacturers like Intel and TI have home-grown ATEs built using in-house tools. They have their own test programs, and only the conversion tools are provided by EDA vendors.
Veerappan explains, “There is no common test program which can test all the chips. You need to customise the program to your chip. Test engineers have to develop the right skills to write efficient test programs.”
Rajiv adds, “Many ATE manufacturers now provide test program development software that are fully graphical user interface based and also automate many development procedures to facilitate faster test program development and minimise programming errors.”
Design of the load board is another critical area. Veerappan shares, “It has to have all the precautions inbuilt. For example, in case of high voltage, it should have a high-voltage cut-off. All types of arrangements are made in the circuit of the load board.”
Test program reuse can significantly reduce the cost and time of testing. Veerappan says, “Reuse is a smart way of reducing time. Currently, 30-40 per cent of the test programs, boards and tools can be reused. Learning of the reuse technique saves a lot of time spent in re-inventing a wheel. It reduces the time-to-market.”
“With rapidly evolving semiconductor technologies, chips go from introduction to obsolescence in less than three years. Obviously, time-to-market and manufacturing cost of new products are extremely important to the company’s bottom line, and one key element that drives both these factors is semiconductor testing. ATE manufacturers need to ensure that the existing ATEs are highly scalable and adaptable to the rapidly changing semiconductor industry,” adds Rajiv.
Ultimate goal: minimise cost and time, maximise yield
The operating speed of ICs has increased greatly. The test systems should be able to match the speed of these faster chips. Another area of development is the manufacturing process technology. As manufacturing moves from 90nm to 65nm process, the tester should be capable of handling the lower footprint and producing reliable test results.
Process technology changes have also had serious effect on the cost of test and the need for test. Kumar adds, “With 32nm technology becoming a reality in 2010, test challenges have only increased. Sub-pico-Farad capacitance measurements and tens of atto-ampere (current) measurements have become essential.”
Today, chips have become very complex incorporating about four million gates. The ATE should be able to test these chips in minimum possible time. You could spend 20 minutes or five seconds to test a chip and every second adds to the cost of chip production. The ultimate goal of any chip manufacturer is to be able to test all the chips in minimal time. This will reduce the cost and increase the yield.
The author is a senior technology journalist at EFY