DCB_Sanjay_Palsamudram
Sanjay Palsamudram, COO, SmartPlay Technologies

AUGUST 2012: For the benefit of our readers out there, could you start by giving them an overview of SmartPlay (SP)?
SP is an end-to-end product design services organisation. To explain a bit more, we design the entire product from the planning end to the realisation end. We started operations in 2008 and have grown to an organisation of 600+ employees in 8 design centres around the the world. We have five centres in India, with the one at Bangalore being the largest and three in the US. We provide services in chip design, digital & analog design and embedded software, primarily in the telecom sector for handsets and infrastructure. We have developed capability all the way from chip design to complete system design which includes software analog and digital design. CyberMedia Research, India,VLSI Design Services Study 2012 recently named us the 2nd largest design services company in India. We feel it’s a vindication of the hard work put in by every single person working with us.

As you mentioned, you have 4 key verticals in your company. Could you tell us what the USP of SmartPlay is?
The design services market in India is a huge one, estimated at around 1.25 billion $. However, playing in the niche area is what we do. In the last 4 years, SP has become one of the largest design services company in India. Today, we have large projects ranging from 65nm down to 22nm technology. Undoubtedly, our USP has to be the talent and experience level of the staff. Given the customer base we have (38 major tech players worldwide), we get to work on truly leading edge technology projects. SP has an inverted pyramid structure as in we have a huge amount of experienced personnel and very few freshers (which may change in the future). As we speak, we have a team in SP working on a 22nm digital complete end to end product test check. We recently completed a 22 nm analog component design for a large IC firm. We can proudly say that where we stand, vis-a-vis working on the latest technology, the air is very thin.

What technologies go into each vertical?
In the digital space, we provide support for our customers working on the newest smartphone technology through communication, networking, connectivity, graphics design and generic processors. Our digital design team works on providing solutions to all these customers. The analog team work on everything from SerDes (Serializer/Deserializer: a pair of functional blocks commonly used in high speed communications to compensate for limited input/output.) to PCI Express, display ports PLLs, low power hi-voltage LDOs, and power management circuits. Today, we are providing test integration and validation for Time Division Synchronous Code Division Multiple Access (TD-SCDMA). It’s a Chinese air interface and worked as an alternative to W-CDMA. Although the name suggests only a channel access method based on CDMA, it is actually the name for the whole air interface specification. We now have great understanding of it and do many turnkey projects and provide solutions for TD-SCDMA air-interface cell phone markets.

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What is the most exciting technology that you are working on right now?
We are engaged with strategic customers in building platforms for their products at IP as well as full chip level. One of them includes a scalable test chip platform right from architecture to GDSII for upcoming process nodes that are below 28 nm. The platform offers a plug and play architecture for testing the memories, mixed signal IPs and high speed IOs. Similarly at IP level we have developed a reusable test bench architecture to verify a highly configurable IP. The complexity can be judged from the coverage points that amount to two lakhs when added for all the configurations. The flow is further extendable for easier integration to SoC level.

Can you enlighten us as to what was most challenging while working on it?
With increasing complexity, the challenges are multi fold. Adding more features while conserving power and die-size to attack the shrinking market window keeps the engineering execution excited. The complete ASIC design cycle is moving to a platform-based approach. Defining such a platform to ensure scalability, maximize re-usability with limited maintenance cost is the foremost challenge that we experience in our latest projects.

Is there any Android related work going on in your design center?
In the embedded software division, we have a very strong android team. One of the leading silicon providers has chosen SP to be one of their partners to provide android based porting solutions to its customers.

What are your views on the evolution of Android?
What Windows is to desktop computing, Android would be to mobile computing. Android started with smart phones and tablets, in future, it would cover pretty much every pervasive and smart devices, this would include TVs, Watches, Eyewear, set top boxes, car infotainment, etc. The primary reason for this is it openness. This has made device manufacturers’ to integrate it as the platform of choice across various form factors and market segments. This again is threatening the survival of Android due to fragmentation caused due to its rapid proliferation.

With such a long list of assignments, I can’t help wonder if you handle all the services in-house?
Yes, we do. We have multiple engagement models with our customers. We have a capacity of 500 people in Bangalore. These teams work from our office to provide solutions to our customers. We develop Offshore Design Centers (ODCs), which is basically an extension of the customers R&D team on our premises. We provide solutions not only from an engineering standpoint, but also compute infrastructure solutions to provide an integrated solution. At times when the customer has to work in close quarters with the employees and provide solutions, we also provide onsite services. We have developed lots of experience in these 3 engagement models and have great comfort in providing solutions in all these spheres.

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You mentioned that chip design was one of your key verticals. Is there any particular segment you focus on?
Well, without doubt our biggest segment would have to be the cell phone and tablet market. We are associates to some of the biggest players in this segment and continue to look at improving by leaps and bounds. In the processors segment, we are among the national leaders in graphic, arm-based and general compute server industry processors. As far as consumer electronics go, we work with video based graphics required for gaming. In Connectivity, we have good experience in fields from TDRS to PCI Express to Ethernet max.

What factor drives performance for next gen mobile processors? We have seen insane clock speeds, multiple cores, and the ever lowering process technologies. Is there something else?
The most significant impact to next gen processors will be in innovative architectures. Certain applications, like imaging/video/gaming, needn’t have the processor to be 100% accurate (unlike mathematical calculations etc). There are novel processor architectures that are propounded wherein the accuracy of the output are traded off for speed, performance and power consumption. Dropping a pixel among millions will not be “visible” to the naked eye but such tradeoffs can have meaningful impact to power, area and performance.

Could you elaborate on some of the design tools you use?
As far as chip design goes – we have licensing agreements with the leading EDA providers viz. Synopsys, Mentor Graphics Metagraphis, Cadence and Magma (recently acquired by Synopsys). So we have EDA tools with top industry leaders to work on both in-house and customer projects.

For a company which undertakes so many projects, your design team must have come across an interesting technical challenge. Could you share it with our readers?
Well, we recently completed a 22nm hi-voltage LDO project for a large company. It required a complete change in system architecture. We could not take a previous generation architecture and then scale it down, especially in analog designs. Our team was responsible from paper specification to the product layout for being put on a shuttle. We had to develop the template; go through several variations and changes and the design team had to come up with very innovative architecture to overcome the technical barrier and meet the original requirements of the LDO. We proposed multiple architecture and after extensive testing closed in on the right one. We finished it and it’s on a test chip waiting for the silicon to arrive and the whole team couldn’t be happier.

Do you see the demand in any product from a specific vertical enjoying tremendous increase?
The obvious answer is Smartphones. The telecom industry has undergone rapid growth. I don’t believe it has saturated yet. In terms of new subscribers and replacement of existing handsets, we still see a great demand and an upward trend of getting the latest phones. Many of our leading customers are in the telecom field and we end up providing them solutions. So specifically for India, the telecom industry has a lot of potential.

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When do you think we will reach a barrier with the current silicon technology w.r.t process technology?
I personally am surprised that Moore’s law is still prevalent and continues to exist. I think with the 20nm requiring double patterning of process technology, I think it has crossed the barrier. It is amazing that even for a 22nm technology, the industry uses 193nm lithography. EUV(extreme ultra violet lithography) is still not prevalent. More than process technology, lithography is becoming a challenge. The whole industry has to move on to EUV. There are already customers pushing us to embrace 14nm technology. When we have to deal with angstroms and atoms to make a difference, that’s when nano electronics and single electron tunneling will come into the picture. I see Moore’s law being prevalent for at least 5 more years (which is a lot w.r.t semiconductor technology).

What kind of fresher training do you provide?
We look for the brightest talents (not necessarily from IITs or NITs only). What we look at is how strong their fundamentals are. We don’t expect people to know everything from the get go, but the important thing is that their attitude be good and they be willing to learn. Secondly, we see how they work in a team, can they mesh well with a team and foster in the industry environment. Finally, the communication skills of the individual is taken into account.

Do you train the freshers in-house?
We have certain training programs in-house which are far superior to those of other IDHs because we have in-house projects and real projects. We have industry production tools available in-house, we have highly experienced engineers and leaders available to guide them. We put them through class room and lab training and real projects before we deem them to be ready for taking on real-time client projects.

You talked about your system being the Inverted pyramid type. Is it because the training is very strenuous?
We want to change the inverted pyramid because there are only so many laterals available in the industry. With the current demand we are seeing, we are hiring exclusive trainers who have industry experience and a passion for training. Our aim is to get 20-40 individuals per quarter trained in different domains ranging from front-end chip design, android to physical design. The ground reality is the demand is more than 5 times the supply, hence the inverted pyramid system is an obsolete concept.


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