AMD today announced the AMD Versal Premium VP1902 adaptive system-on-chip (SoC), the world’s largest 1 adaptive SoC. The VP1902 adaptive SoC is an emulation-class, chiplet-based device designed to streamline the verification of increasingly complex semiconductor designs. Offering 2X 2 the capacity over the prior generation, designers can confidently innovate and validate application-specific integrated circuits (ASICs) and SoC designs to help bring next generation technologies to market faster.
AI workloads are driving increased complexity in chipmaking, requiring next-generation solutions to develop the chips of tomorrow. FPGA-based emulation and prototyping provides the highest level of performance, allowing faster silicon verification and enabling developers to shift left in the design cycle and begin software development well before silicon tape-out. AMD, through Xilinx, brings over 17 years of leadership and six generations of the industry’s highest capacity emulation devices, which have nearly doubled in capacity each generation.
“Delivering foundational compute technology to enable our customers is a top priority. In emulation and prototyping, that means delivering the highest capacity and performance possible,” said Kirk Saban, corporate vice president, Product, Software, & Solutions Marketing, Adaptive and Embedded Computing Group, AMD. “Chip designers can confidently emulate and prototype next-generation products using our VP1902 adaptive SoC, accelerating tomorrow’s innovations in AI, autonomous vehicles, Industry 5.0 and other emerging technologies.”
Confidently Emulate and Prototype Next-Generation Designs
As complexity grows in ASIC and SoC designs, especially with the rapid advancement of AI and ML-based chips, extensive verification of both silicon and software before tape-out is a must.
The VP1902 delivers industry leading capacity and connectivity, delivering 18.5M logic cells for 2X 2 higher programmable logic density and 2X 4 aggregate I/O bandwidth compared to the previous generation Virtex UltraScale+ VU19P FPGA.
Iterate Designs Fast with Unmatched Debug Capabilities
Debug is essential for pre-silicon verification and concurrent software development. Finding and addressing bugs before tape-out keeps programs on schedule and budget. The VP1902 adaptive SoC leverages the Versal architecture, including the programmable network-on-chip, to provide up to 8X 5 faster debugging compared to the prior generation VU19P FPGA.
Development Tools and Ecosystem Collaborations
The AMD Vivado ML design suite provides customers with a comprehensive development platform to quickly design, debug and validate next-generation applications and technologies and accelerate time to market. New features that support more efficient development on the VP1902 adaptive SoC include automated design closure assistance, interactive design tuning, remote multi-user real-time debugging, and enhanced back-end compilation, which enables end users to iterate IC designs faster.
AMD collaborates closely with the EDA community to help customers turn their innovations and technology vision into reality. Working closely with the top EDA vendors, including Cadence, Siemens and Synopsys helps designers access an ecosystem of fully-featured and scalable solutions.
