Arteris, Inc. has announced advancements in its network-on-chip (NoC) technology, enhancing semiconductor designs for artificial intelligence (AI) applications while improving scalability, power efficiency.
The Arteris‘s latest NoC tiling capabilities are integrated with mesh topology support in their FlexNoC and Ncore interconnect IP products. This innovation allows SoCs to expand their performance by more than tenfold without altering the fundamental design, addressing the growing demand for high-speed, robust AI computing.
As AI systems increase in complexity, the modular approach of network-on-chip tiling becomes crucial. This method employs established NoC IP to facilitate scaling, streamline design processes, accelerate testing, and mitigate risks. By replicating soft tiles across the chip, SoC architects can create more efficient designs that are easier to integrate and verify. The innovation primarily targets semiconductor companies, system-on-chip (SoC) designers, and engineers focused on developing cutting-edge AI systems across various sectors, including automotive, consumer electronics, and edge computing.
The NoC tiling and mesh topology advancements are particularly beneficial for integrating AI capabilities into SoCs. As the size and complexity of AI-enabled systems rise, the ability to add soft tiles expedites scaling without disrupting the entire design. This synergy significantly reduces the design time for auxiliary processing unit (XPU) subsystems and overall connectivity, potentially cutting the integration timeline by up to 50% compared to traditional designs.
The NoC tiling architecture organizes network interface units (NIUs) into modular, repeatable segments, enhancing scalability, efficiency, and reliability in SoC projects. These improvements support advanced AI workloads, including computer vision, machine learning, deep learning, natural language processing, and generative AI for both training and inference, even at the edge.
“Thanks to Arteris’ highly scalable and flexible mesh-based NoC IP, our SoC team has implemented support for larger AI data volumes and complex algorithms more efficiently,” stated Srivi Dhruvanarayan, VP, hardware engineering, SiMa.ai. He noted that collaboration with Arteris has enabled the development of a multi-modal, software-centric edge AI platform capable of supporting a wide range of AI models.
K. Charles Janac, president and CEO, Arteris, commented, “Arteris is continuously innovating, and this revolutionary NoC soft tiling functionality supported by large mesh topologies is an advancement in SoC design technology.” He emphasized that this innovation empowers customers to accelerate the development of complex AI systems efficiently while adhering to project timelines and performance targets.
