The device enables routers, switches and line cards to double their bandwidth by transitioning to 112G PAM4 interface rates
Rising data centre traffic driven by 5G, cloud services and Artificial Intelligence (AI) and Machine Learning (ML) applications have led to routers, switches and line cards require higher bandwidth, port density and up to 800 Gigabit Ethernet (GbE) connectivity to handle the load. Several signal integrity challenges need to be overcome as the industry makes a transition to the 112G (gigabits per second) PAM4 Serializer/Deserializer (SerDes) connectivity to support the latest pluggable optics, system backplanes and packet processors.
These challenges can now be overcome with the launch of the PM6200 META-DXTL Ethernet PHY, a compact, 1.6T (terabits per second), low-power PHY (physical layer) solution from Microchip Technology. The solution reduces power per port by 35 per cent compared to its 56G PAM4 predecessor, the META-DX1.
“The industry is transitioning to a 112G PAM4 ecosystem for high-density switching, packet processing and optics,” said Bob Wheeler, principal analyst for networking at The Linley Group. “Microchip’s META-DX2L is optimised to address these demands by bridging line cards to switch fabrics and multi-rate optics for 100 GbE, 400 GbE and 800 GbE connectivity”.
With a high-density of 1.6T bandwidth, space-saving footprint, 112G PAM4 SerDes technology and support for Ethernet rates from 1 to 800 GbE, Microchip’s latest industrial-temperature-grade device maximises offers connectivity versatility for maximising design reuse across applications ranging from a retimer, gearbox or reverse gearbox to a hitless 2:1 multiplexor (mux).
Making full use of the switch device’s I/O bandwidth, the highly configurable crosspoint and gearbox features enable the flexible connections necessary for multi-rate cards that support a wide range of pluggable optics. The PHY’s low-power PAM4 SerDes supports the next-generation infrastructure interface rate for cloud data centres, AI/ML compute clusters, 5G and telecom service provider infrastructure, whether over long-reach direct attach copper (DAC) cables, backplanes or connections to pluggable optics.
Product highlights include:
- Dual 800 GbE, Quad 400 GbE and 16x 100/50/25/10/1 GbE PHY
- Supports Ethernet, OTN and Fibre Channel data rates
- Supports proprietary data rates for AI/ML applications
- Integrated 2:1 hitless mux enables high availability/protection architectures
- Highly configurable crosspoint supporting multi-rate services on any port
- Constant latency, enabling IEEE 1588 Class C/D PTP at the system level
- FEC termination, monitoring and conversion between various interface rates
- 32 long-reach (LR) capable 112G PAM4 SerDes with programmability to optimise power vs. performance
- Support for DAC cables, including auto-negotiation and link training
- Industrial-temperature-range support, enabling deployments in outdoor environments
- Complete Software Development Kit (SDK) with a hitless upgrade and warm restart capabilities and compatible with the field-proven META-DX1 SDK
“For the 56G generation we introduced the industry’s first terabit PHY, META-DX1, and now we have followed with an equally transformative 112G solution that delivers the capabilities system developers need to solve today’s new challenges posed by cloud data centres, 5G networking and AI/ML compute scale-out,” said Babak Samimi, vice president for Microchip’s communications business unit. “By delivering up to 1.6T of bandwidth within a low-power architecture and in the smallest footprint, the META-DX2L PHY doubles the bandwidth of previous solutions on the market while establishing a new level of power efficiency.”
META-DX2L is offered in a small package size of 23 mm x 30 mm, which enables the space savings necessary to deliver the line card port densities demanded by hyperscalers and system developers. Initial META-DX2L devices are expected to sample during the fourth calendar quarter of 2021.
