Memory Design Using Verilog

By Arnav Bansal

Compilation window
Fig. 6: Compilation window

Simulating memory 64-bit×8-bit design

1. Click on Library menu from the main window and then click on plus (+) sign next to the work library. You would see Memory_SP that you have just compiled (Fig. 7)

Start Simulation window
Fig. 7: Start Simulation window

2. In the work library, select as shown in Fig. 7 and click OK. This will open sim-Default window, as shown in Fig. 8

sim-Default window
Fig. 8: sim-Default window

3. Go to Add→To Wave→All items in design options (Fig. 9)

Adding wave to the project
Fig. 9: Adding wave to the project


4. Select the signals you want to monitor for simulation purposes. Select these, as shown in Fig. 10

Selecting and monitoring signals
Fig. 10: Selecting and monitoring signals

5. Selected signals are used to verify data-write operations in the memory. Simulate your design by clicking Run from Simulate menu bar, as shown in Fig. 11

Wave window
Fig. 11: Wave window

Here, to validate the memory implementation, fill the memory at selected address location between 0 and 63. Perform a random data write operation. Enable and read the data from that particular address location.

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Arnav Bansal is an electronics hobbyist who loves to tinker with circuit designs


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