Electronic Design Automation (EDA) is an indispensable tool in coming up with optimised circuits. These are nothing new with engineers as most have worked on one or the other tool. From a simple amplifier design to designing multiple layer PCBs, a lot can be done via EDA. Marco-Casale Rossi, product marketing manager, design group, Synopsys, explains the advances in EDA with, “Today, we can floor-plan hundreds of millions of library instances, or we can place-and-route tens of millions of library instances in less than 24 hours.”
Advances have also been in the form of designing complexity. “The complexity is increasing in all areas of electronic design. In the IC world, we moved from bigger technology nodes to 28nm, 16m, 10nm and now marching towards 7nm. In addition to shrinking nodes we are now packing more and more transistors.” says Ruchir Dixit Technical Director, Mentor Graphics. He further adds, “The designs today perform many more functions than ever before. If we look at the system design world, the scenarios are very similar. Gone are the days of a 4-5 layer board being considered complex. Today’s boards can have as many as 50 layers, very high speed signalling, very large pin out components etc. The leading edge tools allow the electronic designers to design and build these complex systems in an efficient manner.”
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The ever increasing number of EDA tools
Since the emergence of EDA in the late 70’s, EDA quickly evolved into a dedicated industry, and new players keep emerging at regular intervals. Today we have advanced EDA tools like Altium Designer 12, LabView and Virtuoso among others that help engineers come up with the best blueprint for complex circuits.
Aside from the industry established tools, we also have some cloud based tools that have revolutionised the way beginners and hobbyists take up electronics. Cloud based EDA tools like EasyEDA and MeowCAD allow students and hobbyists the ease and freedom to work with the latest libraries while providing updated versions of the softwares, without the hassle of updating user softwares.
Cloud based tools becoming popular
Imagine, working on a tablet, because you don’t have to carry your heavy laptop everywhere. You don’t have to think about the storage or appropriate graphics and processor requirements. All you need is a browser and you are good to go.
Popularisation of cloud based tools has been a significant feature in the recent years. Along with the traditional circuit simulation features, these provide ubiquitous access. This allows the designer to travel light with only the concern for internet speed (which won’t be anything new). Using various advances in website designing, these are now accessible over a wide variety of mobile platforms, including smartphones and tablets.
Cloud based tools also feature quick help via dedicated forums, which provide access to community of like minded individuals working on their own problems. Sharing your project with the developer community and your co-workers over the cloud without having to care for the compatibility of software has also come as an advantage in the cloud based EDA tools.
Flip side to the cloud
However cloud based tools are yet to establish themselves suitable for high precision circuit design. These are more in tune with hobbyists, working on their individual projects or students learning to work on EDA. But for professional purposes, system based tools come to be the better choice.
“An efficient tool should be in a system. This removes dependence on internet while working,” says Sreekanth Tamanna, country manager India, Pakistan, Bangladesh & Sri Lanka, Altium Ltd. The processing time in a cloud based tool is also increased. People working in a closed network have to often update their screens to confirm the latest revisions in their designs. Improved performance, more complex designing, local storage, and better working are some advantages with on system EDA tools.
This might sound like the best alternative, but let’s consider other alternatives before judging a tool. Open source tools have serve some interesting features.
Opening up the source
Open source E-CAD tools are also becoming popular. With the latest releases like Ki-CAD version 4.2, these have become more attractive than ever. With 3D rendering, Github library integration and support for making spice simulation, these are attracting designers bigtime.
Anuj Deshpande, founder Makerville Solutions adds, “we can now make artistic circuits.” He further adds, “We can write script in python and convert to desirable format using Ki-CAD.” Such features certainly make open source tools attractive. Let’s look into some of these features that have cropped up in the recent years.
What are the new features coming in?
On the designers requirement, Neel Desai, product marketing manager, Lynx, strategic alliances and GTS marketing, Synopsys Inc. says, “Design managers need tools that can help them manage complex SoC design projects, monitor their progress and forecast their outcomes.” The Cadence design team came up with massively parallel architecture, physically aware context generation, unified global routing and PPA optimisation in their systems. This involves coordinating the design efforts of multiple engineers and analyzing massive amounts of data, to achieve the fastest and most predictable tape-out possible.
Certified vs. Golden EDA toolsIt is important to understand the subtle but big impact difference between the two classifications. There are many tools that are “Certified” but a minority that are “Golden”. When a semiconductor foundry labels a tool as “certified” it means that it will accept data from a customer if the customer has used the certified tool. These certified tools become a part of the pre-evaluated reference methodologies, also called as RM flow, consisting of suitable tools “Golden” on the other hand means that the golden tool is used – as a reference for other certified tools and as the tool of choice by the foundry for their development tasks. |
3D visualisation
Imagine making a circuit and being able to work on the real time problems, before having to face those problems in real time. Now stop imagining and go for the latest tools and see it for yourself. This option to visualise the full module before possibly destroying copper, comes in very handy at times. “Parameters like heat dissipation can be calculated in the 3D render itself,” says Tamanna.
3D models also help in checking for the final design of the device. The design can be modified to suit the design requirements with a simple 3D render.
Power distribution management
With the latest tools, we can measure the functioning parameters. This helps in checking if the design would work as expected or not. “If the board is getting heated in a particular area, then it has to be designed again,” says Tamanna. This can also help in preventing disaster from striking at a later stage on copper.
Higher precision
With the reducing size of electronics on a daily basis, the requirement for higher precision is also a concern. Earlier people were not concerned with an area of a few mm. “But today designers require very high precision,” adds Tamanna. Today we have requirements for precision at about .1mm. The latest EDA tools support this requirement in order to bring about the best in design.
Digital electronics design also requires very high precision. The current solutions are prepared to support the best in design. “Composite EM technology, in the ADS platform, maintains the same level of accuracy and we have increased the performance by multipleX,” Deepak R K, general manager EEs of EDA, Keysight Technologies India Pvt. Ltd.
Special cases of board design
Wearables and other special use cases, have increased the demand for flexible PCBs. “Rigid-flex is a technology for designers working on flexible PCB,” says Tamanna. With this new feature, the designers can verify the parameters that might interfere with different movement and shape of the product.
The Rigid-flex or Flex PCB boards must perform within the specified performance band in different physical orientations. “It is significantly important to know the exact specifications to which the boards are being designed at. If the designer of these boards does not pay attention to the constraints or the parameters, the board runs the risk of losing its physical or electrical integrity.” explains Dixit. Some Open source tools are also attempting to add such features since wearables often employ flexible PCBs.
Working in Groups?
Dixit says, “Collaboration is not a desire any more but has become a necessity. The designs are getting larger and the design teams are getting more distributed. Multiple engineers can work on their marked/dedicated areas of the same design simultaneously and the updates/impacts of changes in one area are reflected live in real-time to the other engineers.” Today tools offer “live collaboration” for multiple people working in real time. Just hope too many cooks don’t spoil the broth.
“We have the collaboration feature for designers working in groups on a project,” says Tamanna. Open source tools are also updating to the latest features with the group working feature being one of them. “The master-slave mode is for teams working on different levels of the project,” says Deshpande. This can also be used to monitor the progress of the design.
Improving the finer points
Making the interface attractive and easy to use certainly helps and the industry has been working on this direction as well. Deepak says, “In the last year we have focused on making our tools more user friendly.”
With the large number of available components and the minute changes from one component to the next, accurate documentation is also a necessity. Hence, “efficient documentation tools are becoming a necessity,” says Tamanna. The updated tools have automatic schematic and PCB generation, which reduces error due to human intervention.
Taking on the challenges
Certain challenges faced during development can be during designing the circuit, mask preparation, testing the circuit and so on. For circuit designing, Rossi explains it as, “Once the objective is ‘within reach’ we ‘hold’ placement and routing, and systematically ‘change’ the gates: same footprint, different timing, power, temperature inversion point.”
Routing the circuits
Nowadays, hundreds of multi-million instances are packed in a single SoC. It’s practically impossible to do custom / manual routing and hence designers use the EDA tools to do auto routing. According to the Cadence design team, the routing can take anywhere from a few few hours to days, depending on the complexity of the circuit. For such complex SoCs which have billions of transistors, extracting the resistance and capacitance is a Herculean task. Commercially available field solvers do the things automatically once the placement and routing is done during the design phase.
Masking
The primary challenge in mask creation is for semiconductor manufacturers to continue scaling at and below 16/14 nm using 193 nm ArFi lithography equipment. “Until next generation lithography equipment (EUV) is available for production, manufacturers must find techniques to print smaller and smaller geometries with existing equipment,” says Tom Ferry, VP of marketing, silicon engineering group, Synopsys.
He further adds, “Computational techniques modify the design layout to create mask designs that enable lithography equipment to produce patterns on the masks that accurately represent the layout (designer intent).”
Verification and Synthesis
For many years, designers exclusively relied on stuck-at automatic test pattern generation (ATPG) patterns to test ICs. Because delay faults caused by opens and shorts occur more frequently than stuck-at faults, designers gradually began to employ transition delay ATPG patterns to improve defect coverage and lower defective parts per million (DPPM).
According to Chris Allsup, technical marketing manager, sr. staff, RTL synthesis and test automation, Synopsys, “At advanced nodes, process variations give rise to increasingly subtle physical defects that require additional patterns that target more complex failure mechanisms such as partial shorts and partial opens.”
The RTL netlist, in Verilog format is now accompanied by a power intent description, in IEEE 1801 “UPF” format, and logic synthesis has been upgraded to understand power and ground, and to perform optimizations taking into account increasingly complex concepts, such as power/voltage/shutdown islands.
Could there be some database issues?
With the number of EDA tools, the compatibility among tools is another parameter to be considered. On the one hand files from one tool should be able to work with other systems in order for designers to have maximum ease of transition whereas on the other, tools have to be lightweight in order to work efficiently. Rossi puts to rest the database debate with, “There are no simple ‘databases’ in EDA, but rather efficient binary dumps on disks of the in-memory data representation/infrastructure of different classes of tools.”
How would the evolution go from here?
“Today, there is not a “solution of continuity” between our logic synthesis and our place-and-route tools,” adds Marco-Casale Rossi. “Moving forward, the border between logic synthesis and place-and-route will blur, and possibly disappear.”
Chip design is a constant battle against rising process and functional complexity on the one hand, and reducing time to market on the other. Additions like the 5g library for system design according to Deepak, helps innovation in technology as well.
We can hopefully look forward to a design environment that includes the validation of IP, libraries and foundry technology data at the beginning of the process. Support for standard yet adaptable design flows and insights into key project metrics throughout can ease the job of getting chips out of the door and into customers’ hands.
