Friday, March 29, 2024

“Multi-chip packaging, 3D ICs emerging trends”

- Advertisement -

Q. Has 28/20nm semiconductor technology become a major ‘work horse’? What’s going on in that area?
A. It is clear that the semiconductor industry transition to the 28nm family of technologies, which broadly includes 32nm and 20nm, is a much larger transition than we have experienced for many technology generations.

The world’s 28nm-capable capacity now comprises almost 20 per cent of the total silicon area in production and yet, the silicon foundries are fully loaded with more 28nm demand than they can handle. In fact, high demand for 28/20nm has created a capacity pinch that is currently spurring additional capital expenditure by foundries.

As yields and throughput mature at 28nm, the major wave of capital investment will provide plentiful foundry capacity at lower cost, stimulating a major wave of design activity. Cost-effective, high yield 28nm foundry capacity will not only drive increasing numbers of new designs but it will also force re-designs of mature products to take advantage of the cost reduction opportunity.

- Advertisement -

Q. Are you seeing new physical design capabilities including DFR, DP, P&R coming up? Please elaborate.
A. New problems and new solutions continue to arise in physical design and verification. While some, like double patterning, are largely handled by the EDA software, others, like IC reliability checking, require insight by the design and manufacturing organizations.

The Calibre PERC product, which was first introduced in 2010 to attack the problem of verification of ESD (electrostatic discharge) protection, has been applied to a wide variety of other design problems, some of which result in circuit degradation mechanisms that cause failures in the field.

For example, it is used to identify electrical overstress arising from signals crossing multiple voltage domains, and electro-migration issues when interconnects are not sized appropriately for current loads on some nets. It can also be used to check spacing on adjacent interconnects based upon the operational voltage difference. This is used to optimize area while preventing long-term dielectric breakdown.

Other applications, like ensuring design symmetry for transistor drive capacity and impedance matching, are used with cell libraries, memory and analog circuits.

3D IC physical verification challenges are also spurring new physical design capabilities. Since Calibre is a used by the foundries as their design rule manual validation tool, we were confronted with 3D IC issues early on.

That led to a variety of features, now incorporated in Calibre 3DSTAC, to extend verification to multiple chips package on a silicon interposer or stacked with TSV interconnects. As it became apparent that 3D ICs would have unique test requirements, Mentor also accelerated development of software to support both 2.5D and full 3D test requirements over a year ago.

Currently, the primary applications we’re seeing are for silicon interposer based designs and memory chips stacked on processors with WideIO TSV-based interconnects to increase memory I/O bandwidth, and reduce access time and power dissipation.

Q. How do you see the global semiconductor industry progressing in 2013? Has it learned from the previous recession at all?
A. The semiconductor industry went into the last recession in remarkably good shape. Inventories were not excessive and capital spending had been relatively low for several years. That is why the global semiconductor industry was able to bounce back so sharply in 2010 and finally break the $300 billion mark in 2011.

The design boom caused by the current large investment in 32/28/20 nm capacity will inevitably be followed by a period of increased profitability for semiconductor and equipment companies and then a period of more rapid price declines for both semiconductors and electronic equipment. This time, however, the magnitude of these price decreases will probably be muted by the under-investment in semiconductor memory capacity that we are currently experiencing.

Q. What does EDA now need to do at handling 22nm and sub-22nm levels? Is it already happening?
A. As we move toward smaller geometries, we need better techniques to manage the growing problem of variability in nanometer integrated circuit manufacturing. We are really starting to see that DFM (design for manufacturing), something the industry has been talking about for years, is now becoming critical to design.

DFM requires a detailed understanding of OPC (optical proximity correction). Specialists in optics have joined traditional electronic design specialists at EDA companies to create these key technologies. The EDA companies are working closely with semiconductor manufacturers on process technology.

Q. How long will the integration density area savings that you get by going to new nodes remain compelling?
A. Up until now, shrinking line geometries and growing the wafer size have enabled the semiconductor industry to continue to drive down the cost per transistor. But, these two variables are running out of steam. Those of us in the semiconductor industry have always been driven to the ultimate solution for any application, the single chip. But sometimes, the single chip solution is not the lowest cost. Or, even the most reliable or best quality solution.

SHARE YOUR THOUGHTS & COMMENTS

Electronics News

Truly Innovative Tech

MOst Popular Videos

Electronics Components

Calculators