Designing with FPGAs: FPGA-Embedded Processors (Part 5 of 5)

Varsha Agrawal

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FPGA devices are suitable for implementing parallel algorithms. However, sequential algorithms, especially those that do not demand large processing power, are easier to implement as a program in a microprocessor. Many applications require both microprocessor and an FPGA array. One possible way to implement this is to have separate CPU and FPGA chips. But the better approach is to combine them into a single chip. This reduces the power consumption, leads to simple board layout and fewer problems with signal integration and EMI.

CZ6_Fig_1
Fig. 1: Embedded-processor design process
Z23_Fig_2
Fig. 2: The path for project file

This article gives information on FPGA-embedded processors with particular emphasis on the Embedded Development Kit (EDK) from Xilinx. The article also presents an illustrative example of a hands-on experience with the EDK design.

FPGA-embedded processors
There are two types of CPU cores for FPGAs, namely, hard and soft. Hard CPU core is a dedicated part of the integrated circuit, whereas a soft CPU is implemented utilising general-purpose FPGA logic cells.

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Examples of FPGA chips with hard CPU cores include Virtex-4FX and Virtex-5 FXT series with PowerPC cores, and Atmel’s FPSLIC with an AVR core. Some of the soft CPU cores include MicroBlaze and PicoBlaze that are used for the FPGAs manufactured by Xilinx, and Nios II processors that are limited to Altera devices.

MicroBlaze has a proprietary 32-bit RISC architecture and a soft CPU core designed by Xilinx for use in their FPGAs. PicoBlaze has a proprietary 8-bit RISC architecture and a CPU core developed by Xilinx. Nios-II has a proprietary 32-bit RISC architecture and a processor core developed by Altera for use in their FPGAs. It comes in three variants, namely, Nios II/f, Nios II/s and Nios II/e.

BZ2_Fig_3
Fig. 3: Base System Builder
Fig. 4: Custom board selection
Fig. 4: Custom board selection
Fig. 5: System configuration
Fig. 5: System configuration
Fig. 6: Processor configuration
Fig. 6: Processor configuration
Fig. 7: Peripheral configuration
Fig. 7: Peripheral configuration
Fig. 8: GPIO data width
Fig. 8: GPIO data width
Fig. 9: Summary page
Fig. 9: Summary page

The soft processor is typically described in a Hardware Description Language (HDL) or netlist. Unlike the hard processor, a soft processor must be synthesized and fitted into the FPGA fabric. In both hard as well as soft processor systems, the local memory, processor busses, internal peripherals, peripheral controllers and memory controllers must be built from the FPGA’s general-purpose logic.

Fig. 10: Custom board configuration
Fig. 10: Custom board configuration
Fig. 11: System Assembly View
Fig. 11: System Assembly View
DF5_Fig_12
Fig. 12: UCF file

Some of the advantages offered by an FPGA-embedded processor over a typical embedded processor include customisation, obsolescence mitigation, component and cost reduction and hardware acceleration. The embedded-processor-system designer has the complete flexibility to select any combination of peripherals and controllers. In addition, he can design new peripherals to meet any non-standard peripheral set requirement. As an example, if the designer wants six UARTs for his design, off-the shelf processor with six UARTs is not available. However, the same can be implemented in an FPGA easily.

Some of the disadvantages of FPGA-embedded processor include increased tool complexity and design methodology, which require more attention from the embedded designer. Moreover, unlike an off-the-shelf processor, the hardware platform for the FPGA-embedded processor must be designed. If a standard off-the-shelf processor can do the job, that processor will be less expensive in comparison with the FPGA capable of an equivalent processor design. However, if an FPGA is already used in the system, consuming unused gates or a hard processor in the FGPA will make the embedded-processor system’s cost inconsequential.

6C6_Fig_13
Fig. 13: Download.cmd file
BB9_Fig_14
Fig. 14: Export to SDK/Launch SDK

To facilitate FPGA-embedded processor design, FPGA manufacturers offer extensive libraries of intellectual property (IP) in the form of peripherals and memory controllers. Some of the peripherals and peripheral controllers provided include general-purpose I/O, UART, timer, debug, SPI, DMA controller, Ethernet and so on. Some of the memory controllers include SRAM, Flash, SDRAM and Compact Flash.

Embedded Development Kit (EDK)
Embedded Development Kit (EDK) is a suite of tools and intellectual property (IP) that allows you to design and implement a complete embedded processor system in a Xilinx FPGA device. The aim of the EDK is to simplify the embedded-processor design process as it provides an umbrella covering all things related to embedded processor and its design. It may be mentioned here that EDK is specific to the FPGAs from Xilinx.

The EDK comprises two main components, namely, the Xilinx Platform Studio (XPS) and the Software Development Kit (SDK). XPS is used primarily for embedded-processor hardware system development, including configuration of the microprocessor, peripherals and the interconnection of these components, along with their respective property assignments. XPS has a base system builder (BSB) wizard that quickly and efficiently establishes a working design. The wizard is generally used to create the foundation of a new embedded design project.

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79C_Fig_15
Fig. 15: Workspace Launcher
B7B_Fig_16
Fig. 16: Target Hardware Specification
Z8C_Fig_17
Fig. 17: Select Project Template
972_Fig_18
Fig. 18: Xilinx SDK window

SDK is the recommended software development environment for writing the software code for the embedded processors. Fig. 1 shows the embedded-processor design process.

Creating an EDK project
This section discusses how to create an EDK-driven design task to blink eight LEDs on and off at a frequency of 50Hz.

The different steps for designing the blinking of the LEDs are:
1. Open XPS by selecting Start → Programs → Xilinx ISE Design Suite 13.4_1 → EDK → Xilinx Platform Studio

2. From the dialogue box, select Create New Project Using Base System Builder

3. A window will appear titled Create New XPS Project Using BSB Wizard asking you to specify the folder to place the project. Set the desired path. (We have selected C:\edk as shown in Fig. 2.)

4. Then select the interconnect type, either as processor local bus (PLB) or advanced extensible interface (AXI), depending on the FPGA series you are using. As mentioned in the wizard, PLB is a legacy bus standard used by Xilinx that supports current FPGA families, including Spartan 6 and Virtex 6. It will not support new FPGA families. AXI is an interface standard recently adopted by Xilinx as the standard interface used for all current and future versions of Xilinx IP and tool flows. Choose among the two depending upon the FPGA family you are using. We are doing the design using Virtex-5, so we have selected PLB system. Click OK button

5. In the next window select ‘I would like to create a new design’ option and click Next, as shown in Fig. 3

6. A window appears asking the designer to select the board. If you have a standard development board from Xilinx mentioned in the list, select the first option ‘I would like to create a system for the following development board’ and fill in the vendor name as Xilinx and your board name. Otherwise, select the second option ‘I would like to create a system for a custom board’ and fill the board information. The design is being implemented on the ML501 board from Xilinx. As it is not mentioned in the Board Name in the first option, the second option has been selected and the relevant details are filled as shown in Fig. 4. Click Next

7. The next page, that is, the System Configuration page, asks you whether you want to build a single-processor system or a dual-processor system. Select Single-Processor System and click Next (Fig. 5)

8. The Processor Configuration page appears. Select 50.00MHz as the reference clock frequency. The Virstex-5 FPGAs do not have any hard processor, so Base System Builder will set up a MicroBlaze soft processor. Set the system clock frequency as 125.00MHz and local memory as 8kB, and click Next, as shown in Fig. 6

9. The Peripheral Configuration page appears through which we select the peripherals to put in the design. The peripherals will be connected to the MicroBlaze processor via the PLB, and they allow you to control and access features of the FPGA and external hardware. Click the Add Device button, select the IO Interface Type as GPIO and the device as LEDs, as shown in Fig. 7. Click OK

10. Select the GPIO Data Width as 8, as shown in Fig. 8, and click Next

11. Click Next on the Cache Configuration window

12. The Summary page (refer Fig. 9) gives you a summary of the design created by Base System Builder, showing the PLB memory map, peripherals and the files that will be generated

13. Since we are designing using a custom board, the window shown in Fig. 10 appears, indicating that the user needs to update the user constraints file and set the correct position of the FPGA in the JTAG chain. Click OK

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14. The System Assembly View window appears, as shown in Fig. 11. The different regions in the window are explained below for understanding

15. The area marked as (A) contains the project information and has two tabs, namely, Project and IP Catalogue. The Project tab lists the project files like the Microprocessor Hardware Specification (MHS) file, User Constraints File (UCF), Bitgen Options File, iMPACT command file, implementation options file and the ELF file, and the project settings, including the device number, simulation model and netlist type

8C7_Fig_19
Fig. 19: New Source File window

The MHS file defines the hardware components, that is, the configuration of the embedded-processor system, and includes the bus architecture, peripherals, processor, system connectivity and address space. It serves as an input to the platform generator (platgen) tool. The UCF specifies the timing and placement constraints for the FPGA design. The Bitgen Options File contains options for the bitstream generation tool. iMPACT command file is a script file used for downloading bit streams using iMPACT. The IP catalogue contains a list of the peripherals or IP cores that the project has access to. This tab is used when you want to instantiate IP cores into the design.

(B) is the Bus-Connectivity area. It shows the interconnections between the different IP cores, memory and the processor. There are two types of buses, namely, the Processor Local Bus (PLB) and the local Memory Bus (LMB). The vertical line represents a bus and the horizontal line represents a bus interface to an IP core. A hollow connector represents a connection that you can make and a filled connector represents a connection made. To create or disable a connection, click the connector symbol.

(C) is the View-Buttons tab. There are two buttons here, using which you can change between Hierarchical view and the Flat view. Hierarchical view is the default view in the System Assembly View panel in which the information about the design is based on the IP core instances in the hardware platform and organised in an expandable or collapsible tree structure. When you click the directory structure icon, the parts are displayed either hierarchically or in a flattened view.

(D) is the Console Window area. It displays all the textual information, warnings and errors that occur as the changes are made to the project, netlists and bitstreams, etc.

(E) is the System Assembly View in which you can view the project’s IP cores and the properties. It displays all hardware platform IP instances using an expandable tree and table format. The IP elements, their ports, properties and parameters, which are configurable in the System Assembly View, are written directly to the MHS file. There are three tabs in the System Assembly View, namely, the Bus Interfaces, Ports and the Addresses. The bus interface tab shows the following information for each core:

(i) Instance name (name of the core used to reference the core in the UCF)
(ii) Bus name (the bus to which the core is connected)
(iii) IP type (name of the IP core as in the IP catalogue)
(iv) IP version (the version of the IP core)

The Ports tab shows the user accessible ports of the IP cores and the nets to which they connect. The Addresses tab shows how the IP cores are mapped to the PLBs in the design

(F) is the Filters Pane area. It allows you to filter what is shown in the System Assembly View for simplified view of the design or in the case of many IP cores in the design.

16. Since we are using custom board for designing, the UCF file needs to be updated. Allot the FPGA pins to the LEDs, Clock and RST signals. The UCF file created for the ML501 board is shown in Fig. 12.

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17. The download.cmd file is changed, as shown in Fig. 13, as the FPGA is the 4th device in the JTAG chain used. (The number assigned depends upon the JTAG being used.) Save the project

18. From the XPS menu, select Project → Export Hardware Design to SDK

19. In the dialogue box that appears (Fig. 14), make sure that Include Bitstream and BMM File are ticked and click Export Only

20. The bitstream will be generated and the project will be exported to SDK subsequently. Once it is done, we can progress to the next step

21. Open SDK by selecting Start → Programs → Xilinx ISE Design Suite 13.4_1 → EDK → Xilinx Software Development Kit

22. The first thing that the designer has to do is to enter the SDK workspace. SDK workspace is a folder wherein the software application(s) for a particular EDK hardware design are managed. The folder specified is shown in Fig. 15. You can choose any folder but it is better if the software folder is created inside the main project folder for ease of use

23. SDK opens with a Welcome screen. Select File → New → Xilinx C Project. Next, you have to specify the hardware platform. Click Specify on the window that appears. In the dialogue box that appears, type the name of the project as edk and use the Browse button under the Target Hardware Specification (refer Fig. 16) heading to navigate to C:\edk\SDK\SDK_Export\hw\system.xml file. Click Finish

24. The wizard that follows allows you to create a template software application for the project. The default is ‘Hello World’ example. We want to create a blank application. Select Empty Application and click Next, as shown in Fig. 17. Click Finish

25. An SDK window appears as shown in Fig. 18

26. In the Project Explorer, open the tree empty_application_0 → src. There is no source file in the folder. We need to add the source file. Select src folder and go to File → New → Source File. In the dialogue box that opens, specify the name of the source file to be created and the folder in which to put it, as shown in Fig. 19. Click Finish. If you now expand the src folder, you will find led.c inside that folder

27. Click on led.c and paste the code given below onto it. Save the file. When you save the file, it is automatically compiled. You should get zero errors, as shown in Fig. 20

C1C_Fig_20
Fig. 20: Program compilation

Download Source Code: click here

The C code first initialises the LEDs port and then sets the port as output port. Then the LEDs are switched on and off using a delay created by the ‘for’ loop

 

#include “xparameters.h”
#include “xgpio.h”
#include “xutil.h”
//===========Program===========//
int main () {
unsigned long i;
//Init LEDS
XGpio LEDS;
XGpio_Initialize(&LEDS, XPAR_LEDS_
DEVICE_ID);
XGpio_SetDataDirection(&LEDS, 1,
0x00);
//Out
while (1)
{
XGpio_DiscreteWrite(&LEDS, 1,
0xFF);
for (i=0; i<0xF0000; i++);
XGpio_DiscreteWrite(&LEDS, 1,
0x00);
for (i=0; i<0xF0000; i++);
}
return 0;
}

Select Xilinx Tools → Program FPGA. The bitstream gets loaded to the FPGA. The LEDs start blinking. If they do not blink, press the reset switch used in the design. On pressing the reset switch they will start blinking.

Conclusion
With this part, the series of articles on Designing with FPGAs is concluded. The articles were written with an aim to provide the electronics engineers, professionals and hobbyists an insight into different aspects of system design using FPGAs.


Varsha Agrawal is a scientist at Laser Science and Technology Center (LASTEC), a premier DRDO lab working in the field of laser-based defence systems. She has more than 13 years of R&D experience in the design and development of a variety of systems for defence-related applications. She has authored two books and published more than 20 research papers and technical articles

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