7nm IC Technology Trends And Challenges (Part 2 of 2)

By V.P. Sampath

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In the previous part of this article we started learning about the trends and challenges of 7nm IC technology. Let us learn more about the same.

How EUV is different from older lithography technologies

There are multiple ways that extreme ultraviolet (EUV) differs, mostly associated with the methods to create and transport the short-wavelength light. Traditional lenses cannot be used with EUV as these absorb light. A mirror with a highly-specialised coating, called a multilayer mirror, must be used. Even these special mirrors absorb about 30 per cent of light, so it is advantageous to use as few as possible. Any gas in the light path, such as air or nitrogen, will also absorb the light, thus, the entire light path is inside a vacuum chamber.

While source power is the chief concern due to its impact on productivity, significant changes in EUV mask infrastructure, including blanks, pellicles and inspection, are also under study. Particle contamination would be prohibitive if pellicles were not stable above 200W, the targeted power for manufacturing. Without pellicles, particle adders would reduce yield, which has not been an issue for conventional optical lithography with 193nm light and pellicles.

Current lack of any suitable pellicle material, aggravated by the use of hydrogen plasma cleaning in EUV scanner, is preventing the adoption of EUV lithography for volume production. Some issues not specific to EUV such as resist collapse and stochastic effects (including photon shot noise) also currently bar EUV from exceeding resolution limits of immersion lithography in high-volume manufacturing.

EUV lithography
Fig. 5: EUV lithography

Double patterning is expected for EUV for random logic patterns at 7nm node (32nm pitch) due to the need for dipole illumination. 5nm node (22nm pitch) would likewise be expected to use multiple patterning already being developed for immersion lithography. However, IBM must hope it can reduce the cost by the time 7nm chips are ready to be manufactured in a few years.

IBM is expected to go beyond 7nm by the end of the decade, but it also recognises that it will be a much harder task. Scaling to 7nm and below is a terrific challenge, calling for deep physics competencies in processing nano materials affinities and characteristics. New materials such as carbon nanotubes or graphene will be necessary to go beyond 7nm. The alternative could be to start developing other types of computers such as quantum, cognitive or neuromorphic.

Currently, state-of-the-art lithography has a wavelength that is 193nm wide, which makes it quite difficult to design chips with much smaller transistors. EUV lithography, on the other hand, has a wavelength of only 13.5nm. EUV lithography is still much more expensive to use because it must operate for longer periods of time and is sensitive to the smallest vibrations when designing chips.

Self-aligned quadruple patterning

As 193nm immersion lithography is reaching its optical resolution limit using single exposure, advanced multi-patterning concepts are being studied to reach lower nodes. Targeting the node, self-aligned quadruple patterning (SAQP) is an advanced patterning approach that uses pitch splitting to extend the capability of double-patterning 193nm immersion lithography. Using parallel interpretation of multiple scatterometry targets with slightly variable pitches, researchers have revealed that scatterometry is capable of measuring different space populations, and developed metrology solutions can be utilised to monitor and control each process step of SAQP patterning.

Next-generation transistor is called nanowire FET, which is FinFET turned on its side with a gate wrapped around it. Nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by International Technology Roadmap for Semiconductors. It has paved the idea of making switch-in-transistor architectures down the road and is developing technologies in the arena.

Chipmakers see a path to extend today’s FinFETs to 7nm, but 5nm is far from certain and it may never happen. Indeed, there are a multitude of technical challenges at 5nm. And the cost for 5nm is expected to be astronomical. Performance and cost concerns are the big challenges in scaling to 5nm, and addressing these will involve extension of current approaches as well as introduction of new technologies and materials. If the industry moves forward with 5nm, and so to help the industry get ahead of the curve, semiconductor engineering has assembled a list of some of the more challenging process steps at 5nm.

Patterning and mask making

For 7nm and beyond, patterning is the biggest challenge. This technology has to be production worthy, with the right uptime of tools and an economic throughput per day. In theory, EUV simplifies the patterning process. With 193nm immersion and multiple patterning, there are 34 lithography steps and 60 metrology steps at 7nm. This compares to just six lithography steps and seven metrology steps for 28nm. With EUV, there are just nine lithography steps and 12 metrology steps at 7nm. Even so, chipmakers still require both EUV and multiple-patterning at 7nm and beyond. And ultimately, the decision to put EUV into production depends on the maturity of the power source, mask infrastructure and resists.

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