A wealth of opportunities for semiconductor manufacture ing are becoming available in the ‘more than Moore’ 2.5D/3D world. Yole Développment of France expects the shipment volume of 3D IC wafers to reach 10 million units in 2012. The semiconductor ecosystem, comprising design-houses, fabs and foundries, assembly and test providers, EDA developers and research institutes, needs to go through a learning curve as it is now necessary to have an ecosystem optimised for converting such technologies into high-volume manufacturing.

At the SEMICON Singapore 2012 event, Dr Ho-Ming Tong, GM and chief R&D officer of the Advanced Semiconductor Engineering Inc. (ASE) Group, the world’s largest provider of independent semiconductor manufacturing services in assembly and test, commented: “Despite progress in 3D-IC development over the years, challenges remain in the areas of cost control, design, mass production and testing in the lead-up to commercialisation. Given the readiness of silicon interposer-based 2.5D-IC technology to move to the next stage, its deployment will expedite migration from the 40nm node to 28nm. With computing and smart devices fuelling the growth of the market, commercialisation of 2.5D and 3D ICs may take place in 2013.”

Tezzaron 3D IC devices (Image courtesy: www.electroiq.com)
Tezzaron 3D IC devices (Image courtesy: www.electroiq.com)

To address the challenges of taking 2.5D/3D systems to high-volume manufacturing, collaborative partnerships are very critical.

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“IME has established strategic partnerships with leading players in the semiconductor ecosystem to co-develop cost-effective 3D-IC integration and process technologies in Singapore. Our new 300mm advanced packaging facility will provide deeper and broader capabilities to our partners to overcome the challenges in 3D IC,” informed Prof. Dim-Lee Kwong, executive director of the Institute of Microelectronics (IME)—a research institute of the Science and Engineering Research Council (SERC), Agency for Science, Technology and Research (A*STAR).

James Amano, director, International Standards, SEMI, USA, announced during SEMICON West 2012 that the SEMI 3DS-IC Committee, formed in late 2010, had approved its first standard for publication. Pending successful procedural review, the document will be published as “SEMI 3D1, Terminology for Through-Silicon Via (TSV) Geometrical Metrology.”

SEMI 3D1 will provide a starting point for standardisation of geometrical metrology for selected dimensions of TSVs. The Inspection & Metrology Task Force recognised the need for such a standard because although different technologies can measure various geometrical parameters of an individual TSV or an array of TSVs—such as the pitch, top diameter, top area, depth, taper (or sidewall angle), bottom area and bottom diameter—it is currently difficult to compare results from the various measurement technologies as parameters are often described by similar names but actually represent different aspects of the TSV geometry. SEMI 3D1 is an important first step in promoting common understanding and precise communication between stakeholders in the 3D-IC manufacturing supply chain.

Challenges with 2.5D/3D technology
The challenges in moving to 2.5D/3D technology relate to design, fabrication, assembly and testing of 2.5D/3D ICs.

Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems (India), says, “With the accelerating demand for higher bandwidths, low power and mounting density, a lot of IC design teams are trying to adopt 3D-IC technology with TSVs. 3D ICs not only promise improved performance and reduced costs but also assure ‘more than Moore’ integration by packing a great deal of functionality into small form factors. While 3D-IC holds a lot of promise, it is still evolving and has design and verification challenges which need to be addressed.”

3D ICs with TSVs do not need a new 3D design system for digital design, analogue/custom design and IC/package co-design, but they do need some new capabilities. They also require the following for a successful interconnection of 3D-IC dies:

1. As redistribution layers (RDLs) are typically formed on the back of the die, bumps can be placed on both front and back.

2. TSVs can be drilled between the first metal layer and the back-side RDL. These may have a diameter of 1 to 5 microns.

3. Micro-bumps (much smaller flip-chip bumps) have to be aligned to create a data path from one die to another.

Ahuja cites some of the challenges involved:

System-level exploration. System-level exploration for 3D-IC TSV technology is a convergence of silicon and packaging with the design, making it possible to conceive and design new architectures. To fully benefit from 3D-IC TSVs and make this technology cost-effective, different 3D architectures need to be considered and evaluated at a very early stage.

Existing system-level exploration tools can provide early power, area and cost estimates, and allow what-if explorations across architectures, silicon IP choices and foundry processes. However, these tools need to be extended to serve stacked die implementations, package and manufacturing considerations, as well as provide some guidance on tradeoffs that system houses would have to make between cost, power and performance.

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3D floorplanning. 2D floorplanning is complex enough in today’s giga-scale designs. Adding a third dimension makes floorplanning even more challenging. Since TSVs can be very large compared to logic gates (they add more wire length and extra coupling, which is mitigated by keep-out zones that add area), a TSV-aware 3D floorplanner must allocate optimised TSV resources with respect to logic gates.

3D implementation. Synthesis, placement and routing for 3D ICs bring forth a number of new considerations. For example, there are new layout rules that may be driven by features on the adjacent die. The back-side RDL is a new layout layer. Given their size, TSVs themselves are a significant new layout feature. An implementation system that supports 3D ICs must be made ‘double-sided aware,’ taking into account both the top and bottom of each die. This may call for a new modelling and database infrastructure, TSV-specific tools and support for a variety of stacking styles.

3D extraction and analysis. Extraction and analysis is already challenging in a 32nm 2D scenario, but this design convergence is even more complicated with 3D ICs. Existing extraction and analysis tools must consider RLC parasitics for TSVs, micro-bumps and interposer routing. Also, they must be made 3D-aware. Timing, signal integrity, power and thermal gradients must be analysed across multiple dies and packaging taken into consideration.

Signoff raises new questions with 3D-IC stacks: When is the right time to sign off? What are the appropriate signoff points? Can design rule check (DRC) and layout-versus-schematics (LVS) run on the entire stack? Should and can timing be verified for the entire stack? Is there any crosstalk between dies? Finally, electromagnetic interference (EMI) is a potential concern for 3D ICs and a consideration for analysis tools.

3D DFT. Design for test (DFT) for 3D ICs is even more critical than for 2D ICs. While wire-bonded systems-in-package (SiPs) may have a few hundred interconnects, 3D ICs may have thousands. Even a single defective TSV can render an entire stack unusable. If individual TSVs have 99.9 per cent yield, at least one defective TSV can be expected in a stack of 1000 TSVs.

To provide test generation, the wrappers should support the internal testing of each die as well as all the inter-die interconnect logic and TSVs. In addition to the traditional fault models used for digital testing (stuck-at, transition, stuck-open, bridge faults), 3D ICs require specific interconnect fault models to test the TSVs and micro-bumps. For designers, this means that in addition to expanding EDA tools to be 3D-aware, they have to start thinking in 3D.

Joseph Sawicki, VP and GM, Design to Silicon Division, Mentor Graphics Corp., elaborates: “In the area of digital physical design (place and route), the challenge of 2.5D is mainly creating silicon interposer (SI) layouts. Interposer design must address pin-out, bump placement, support for 45-degree and tapered routing, and length matching to control timing and parasitic capacitance in passive interposers. Some modest extensions are needed to adapt IC P&R tools for this task.

“On the other hand, there are a variety of impacts when considering full 3D design, starting with floor planning and cell placement. Block partitions need to consider multiple constraints such as TSV location, connectivity, area and congestion when deciding how blocks will be realised on different dies. Placement needs to be done in three dimensions considering the vertical plane assignment of standard cell/macros to minimise wire length and via count. Clock tree synthesis and routing must try to minimise congestion using TSVs, and it is critical that clocking is balanced across planes as well across each die.”

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3D IC stacking (Image courtesy: www.i-micronews.com)

According to Sawicki, for 2.5D, DRC and LVS verification challenges are relatively modest. Dies are developed/verified using the existing design and verification flows. Then the die interfaces, usually silicon interposers, are designed and verified using a similar flow with some enhancements to handle multi-die pin-out naming checks. Parasitic extraction tools are being enhanced to handle silicon interposers, front and backside metal layers, and inter-die coupling, which require new models for these elements. For full 3D (stacked die with TSVs), there are lots of new challenges such as thermal modelling (including the impact of IR drop), power network integrity, stress modelling, and modelling of the parasitic effects of TSVs interacting with each other and with transistors in active die areas.

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In the test area, the biggest requirement is providing known-good-die (KGD) to the 2.5D or 3D assembly process in order to ensure a profitable yield. The term ‘KGD’ means more comprehensive testing needs to be used during wafer-level testing. For 3D (stacked die) in particular, the test access infrastructure for routing test data and results to and from any of the dies within the vertical stack is a critical need.

This is a new requirement because all but the bottom dies have connections only to their immediate neighbours and no direct access to package pins. A dedicated access infrastructure must be incorporated within each die of a vertical stack in order to route test data and results up and down the stack. Since the bare die may come from different sources, standardisation of this infrastructure will be needed to ensure proper interoperability between all dies. The IEEE P1838 working group is currently developing such a standard with direct involvement of Mentor.

Sawicki shares: “Multi-die scenarios also create the need for system representations that can accurately represent new elements in a consistent manner, and allow rapid prototyping and optimisation across multiple dies. The EDA solutions for 2.5D (interposed based) are well in hand and do not pose a technology barrier. Full 3D (chip stacking with TSVs) for homogeneous designs (e.g., processors or other logic systems split across multiple dies) is another matter. That will definitely require significant EDA development and some re-architecting of the design tools. These tools are now in development and are expected to be available when the market demand materialises.”

Collaborative effort required
Some kind of collaborative approach is essential to harness 2.5D/3D-IC technologies successfully.

Ahuja explains: “Collaboration and building a well-defined ecosystem are crucial for successful design and usage of 3D ICs. To support 3D IC for EDA tools, there are additional components which need a deeper level of understanding. Optimising system cost with the shortest possible turnaround time is a major challenge which is not possible without an integrated approach to 3D-IC design. Since many 3D stacks combine digital and analogue/RF circuitry, a strong analogue/mixed-signal capability plus a robust IC/package co-design capability and PCB layout system are critical for providing a ‘complete’ 3D-IC realisation methodology.

“3D-IC design should be a shared effort among system architects, package designers, IC designers of various dies, PCB designers and DFT engineers. That calls for a system that can handle the handshake between different platforms, close collaboration between different design environments, and co-design among groups that have historically worked separately. Handoffs between the same company’s designers are difficult enough, and 3D-IC die handoffs could be between different companies or participants in the ecosystem.”

According to Ahuja, while EDA tools can help minimise some of these interactions by providing a common platform, the overall design task gets challenging when dies come from different places and are implemented in different environments. A proper handoff point must be agreed upon by the industry to make it easier for IC designers to exchange design data. Therefore collaboration within the ecosystem becomes crucial.

Standards development activities are going on at the Silicon Integration Initiative (Si2), SEMI and Sematech. The IEEE P1838 Test Working Group is working on 3D-IC DFT architectures. In the memory domain, there is a lot of activity going on at JEDEC, which has ratified the wide input/output (I/O) memory standard. Micron and Samsung have jointly announced formation of the High density Memory Cube (HMC) Consortium, which seeks to develop HMC memory stacks that can be integrated into 3D-IC systems.

“Cadence has invested significantly in ecosystem collaboration for 3D ICs. It has worked with IMEC on DFT architecture, which was later given to the IEEE P1838 working group. Cadence is a working member in Si2 3D TABs on power, thermal and path finding. It is closely involved with GSA 3D-IC working group efforts to bring collaboration in the industry in terms of business models and other topics. Cost-effective, adoptable technological evolution and ecosystem collaboration are essential for bringing 3D ICs with TSVs into the mainstream,” Ahuja shares.

Key issues limiting 3D TSV HVM and need for standardisation
According to Ahuja, one of the biggest questions for any new memory technology is whether there is an industry structure to support it. Industry efforts are underway to standardise wide-I/O DRAMs in the areas of performance, protocol, number of banks and channels, and number and arrangement of TSVs. Such standardisation will create a viable market in which DRAM manufacturers can sell their standard dice to multiple customers. For their part, customers will have multiple compatible devices to choose from. Therefore standardisation is key to the growth of 3D ICs.

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One of the concerns regarding TSVs’ application with memory, in particular, is that DRAM performs poorly at junction temperatures above 85ºC. Keeping the memory contents refreshed at higher temperatures requires more current, which itself leads to more heating of the die. There are limits to what can be standardised, and many of the issues around assembly, test and heat dissipation from the 3D-IC stack will need to be addressed by each customer.

Assembly continues to be a major concern in the industry. Many of the processing steps involved in creation of TSVs can create mechanical, thermal or electrical stresses on the die being processed for TSV. These stresses may change the properties of the device.

Manufacturing test is another issue. For example, finding a method to probe TSVs with a diameter of 10 mm each and on a 50mm grid could prove problematic. Allowing the probe head to contact more than 2000 TSVs at a time without damage is another example. As the industry works to resolve these issues, we will surely see logic devices with TSV-connected DRAM in the next few years.

Leading applications for 2.5D/3D ICs
“One of the initial applications for 2.5D is large FPGAs. For example, Xilinx’ stacked silicon interposer solution, which was announced in 2010 and began shipping in December 2011. 2.5D is also being used for integration of memory with CPUs in complex, multi-die SoCs. The motivation is higher communication bandwidth with memory, overall lower system power consumption and smaller footprint. Semico has indicated that large pitch interposers also have opportunities in applications such as MEMs and RF,” shares Sawicki.

“Semico also reports that initial full 3D products using TSVs are appearing in camera and memory products. Toshiba is making a TSV camera module for cell phones that was introduced before CES in January 2012, and Samsung released engineering samples in August 2011 for a DRAM module using TSVs. For the most part, 3D-IC technology is still evolving and expected to enter high-volume production in the next three to four years. For example, Samsung and Micron have joined hands to create a consortium for what they call the hybrid memory cube. This consortium is designed to create standards that will allow development and adoption of 3D technology for stacked die memory modules.”

One key question is, “Does the learning curve involve re-adjustment of roles and responsibilities in the manufacturing flow?” According to Sawicki, there are some interesting interactions between IC design and packaging groups and their roles, depending on who gets the assignment to design the overall 2.5D/3D assembly. If an IC design group gets the assignment, it uses IC design tools; if packaging group gets the assignment, it tries to use packaging tools/methodologies, driving some interesting new product requirement discussions.

“There is still much discussion on whether the foundry or OSAT will own wafer thinning and stacking and test. One new constraint is that whoever owns the stacking process will also have to own test as he will need to ensure KGD as well as support any partial stack testing,” he adds.

Future trends
Talking about the future 3D-IC technology trends, their timeline and impact on EDA, Ahuja shares: “Despite the lingering challenges and unanswered questions, the semiconductor industry is starting to work on the wealth of functionality and performance that 2.5D/3D IC promises. According to Yole Development, the shipment volume of 3D-IC wafers will touch 10 million units in 2012. Designers and engineers can now build and design energy-efficient and better-performance systems using heterogeneous technologies such as MEMS, CMOS and silicon photonics through the enablement of 2.5D and 3D-IC technology.

“Memories and sensors markets are anticipated to provide the largest market owing to the growing demand for enhanced design methodologies that can be used in a wide variety of applications. Among the application sectors, consumer electronics segment largely adds to the overall evolution of the market. In the forthcoming days, it is likely that newer applications such as hybrid memory, graphics processor unit, low-density parity check decoder and cell broadband engine will rise to serve as prospective markets for 3D ICs and TSV.”


The author was executive editor at EFY till recently

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