5C9_arbind_ppLatches are something in your design which always needs attention. There are tools that help designers pin-point existence of latches in their design as ‘must know’ information. And then, it is the designer’s responsibility to correct if the latch usage is unintentional, as this could easily have happened due to poor RTL coding practices.

Once the latch existence is acknowledged at synthesis level, then the downstream tools follow those conventions. This statement is suitable for ASICs, but latch existence is not acceptable for FPGAs. It would be fine to say that FPGA tools have more accurate timing analysis for the flop-based designs.

An expert designer knows how to utilize the time-borrowing capability of a latch for slack balancing while optimizing latch based critical paths in the design. Once he or she decides to use latches in a particular design, the engineer has to make sure that the enable signal is stable and valid data is being captured in the latch. This helps to avoid unstable states in the design.

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Here are few differences between Latch Vs Flip-flop for your reference below:

Latch is transparent – because input is directly connected to output when enable is high. It means Latch is sensitive to pulse duration (also called soft barrier)Flip-flop is a pair of latches (master and slave flop). Flip-flop is sensitive to pulse transition. The signal only propagates through on the rising/falling edge (also called hard barrier)
Less Area (less gates)More Area (more gates) because flip-flop contains two latches.
Less Power (less gates)More Power (more gates)
Fast –
(The longer combinational path can be compensated by shorter path delays in the subsequent logic stages. That’s why, for higher performance, circuits designer are turning to latched based design.)
Slow –
(The delay of a combinational logic path of a design using edge-triggered flip-flops always less than the clock period except for those specified as false paths and multiple-cycle paths. Hence the longest path of a design limits the circuit performance.)
Require more tool manipulation and more hand-calculations to verify that they meet timingEasy to check design timing using Static Timing Analysis (STA) tools
Cycle-borrowing to gain more setup time on the next register stage, as long as each loop completes in one cycle

To meet the timing in the design, Designers consider latches to adjust timing mismatch.

Data launches on one rising edge, so it must setup before next rising edge. If it arrives late, system fails. If it arrives early, time is wasted due to hard edges in Flops
For ASICs with large clock skew, latches have substantial benefits for reducing the clock periodEven for the high speed pulsed flip-flops with zero setup time, as they are not transparent, the impact of the clock skew is not reduced
Level-sensitive latches reduce the impact of inaccuracy of wire load models and process variation.Flip-flops demands for the highly accurate wire load model and process
In DFT, Latches needed as a lockup state at the clock domain crossings in the scan chain to avoid unpredictable behaviorIn DFT, use flops that can be scanned (controllable and observable)
In FPGA, level-sensitive transparent latches should be avoided in FPGAsIn FPGA, edge-sensitive flip-flops are used exclusively. Timings analysis is more appropriate with flops for FPGA tools
Circuit analysis is complex. You may see last minutes timing mismatch surprises at the implantation stage.Circuit analysis is easy
High-speed microprocessor designs typically use master-slave latches instead of flip-flops so that logic can be added between the rising and falling clock edges.

Most of these companies have written their own specialized STA tools to verify latch-based designs.

The most commonly used flop in the design world is D type flip-flop.

FSM implementation mostly involves D Flip-flops due to minimum number of logic gates and lesser cost as compared to other types of flip-flops.

For non-timing-critical configuration registers, latches work great, due to fewer gates and less power consumptionFor non-power aware design, Flip flops are preffered over Latches
Latch is an asynchronous block. Therefore you must ensure that the combinational functions, which generate input signals for the latch, are race-free. Otherwise they may generate glitches, which may be latched, causing hazards in your system.A flip-flop, on the other hand, is edge-triggered and only changes state when a control signal goes from high to low or low to high
Latch based design is noisy, because any noise in the enable signal disrupts the latch output easily.Flip-flop based design is robust

About the Author
Arbind is a Core Competence Applications Engineer with Atrenta. He has eight years of experience in VLSI design specializing in RTL checking and optimization. Arbind has an M.Tech in VLSI Design from IP University, New Delhi. Arbind has authored many technical papers and articles on different topics for various conferences and publications. Email: [email protected]