7nm IC Technology Trends And Challenges (Part 1 of 2)

BY V.P. Sampath

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The nanometer (nm) process world is a great mess. Today we see 350nm to 90nm in declining mode, 65nm to 32nm still moving towards maturity and 22nm to 14nm in growth mode. If we extrapolate this trend to 7nm and then 5nm and 3nm beyond 2020, we can envision that, by that time 14nm and 10nm will be in major production. Fin field effect transistor (FinFET) process will be perfected with 16nm, 14nm and 10nm, which will be adopting the same technology with improved performance.

Single-transistor 7nm-scale devices were first produced in early 2000s; commercial production of 7nm chips is still at a development stage. Most semiconductor production equipment being used for fabrication of 10nm chips are used for 7nm manufacturing. 7nm chips are 10 to 15 per cent faster than 10nm chips, while reducing power consumption by 35 to 40 per cent.

A nanometre is a billionth of a metre. In the next six years, manufacturers plan to make chips with features measuring from 100nm to 70nm, using deep ultraviolet light of 193nm and 157nm wavelengths. Silicon has already managed to fabricate FinFET transistors using InGaAs and InP on a 300mm 22nm silicon wafer a year and a half ago.

7 nm IC technology
Fig. 1: Nanometer technology profile

Thanks to the silicon-germanium process, we may soon witness the first functional transistors with 7nm technology. The fundamental flaw with silicon transistors is that, at 7nm point the transistors sit so close to each other that an effect called quantum tunneling occurs. This effect unfortunately means that the transistor cannot be turned off reliably and for the most part will stay on. So the physical limitations of silicon are very real and, in fact, insurmountable.

One alternative is to find a material that can physically scale down past silicon or can achieve faster switching speeds. The other is to rely on something other than electricity to achieve/read on or off states, such as light. However, there is one very promising short-term silicon alternative that will most likely supersede silicon in a few years.

III-V semiconductors, which were originally expected to debut at 10nm, are now being pushed back to 7nm or 5nm due to ongoing manufacturing difficulties. Chips suffered from lengthy delays due to tick-tock manufacturing schedules. Foundries have managed to create the world’s first working version of a 7nm chip, which promises to be twice as dense as next-generation 10nm chips, and even denser than today’s 14nm chips. This breakthrough should enable the building of chips that have more than 20 billion transistors. Creation of the working samples of chips with 7nm transistors is achieved by moving away from pure silicon to silicon-germanium alloy for making the transistors.

The new material has higher electron mobility and makes it possible to have faster switching transistors and lower power requirements. Light is directed onto a mask, which is sort of a stencil of an integrated circuit pattern. Image of that pattern is then projected onto a semiconductor wafer covered with light-sensitive photo-resist. Creating circuits with smaller and smaller features requires shorter and shorter wavelengths of light.

Technology node

In semiconductor manufacturing, we define the 7nm node as the technology node following the 10nm node. Node is merely a label for a group of technologies that deliver an improvement rather than a measure of half-pitch or gate length. The term node is used by the semiconductor industry to characterise major targets in their manufacturing roadmap.

Transistors involve fin-shaped pieces of silicon, where each fin is about 14nm wide, 60nm to 70nm tall and 100nm or longer.

Gate-all-around FETs are the most likely approach at 7nm, with germanium as a channel option, which assumes that certain difficulties of adapting germanium for n-channel can be overcome. Currently, germanium is an excellent p-channel material but more difficult to work with for n-channel. Slow caches can recognise substantial gains over 28nm, but fast cache scarcely improves over the current generation. If gate-all-around and other technologies get perfected by, say, 2025, these may take over by 2030.

In any case, there are two basic transistor candidates at 7nm: FinFET and lateral gate-all-around nanowire FET, sometimes called lateral nanowire FET. At 5nm, the industry is leaning towards lateral nanowire FET. For 7nm FinFETs, chipmakers need to make the fins taller to boost drive current. FinFETs also have new channel materials to boost mobility.

Fig. 2: Gate-all-around FET

The second option, lateral nanowire FET, is basically an evolutionary step from FinFET. It increases the gate area, so that you are more effective at turning off the device.

Nanowire FETs provide better electrostatics than FinFETs, but nanowire FET is more difficult to make in a fab. Still, FinFET and nanowire FET use many of the same process steps. One of the main differences is that nanowire FETs require complex processes on the bottom of the device. For 5nm, or even for 7nm, foundry experts are gearing up to develop further next-generation transistors; front runner among these seems to be what is called gate-all-around transistor.

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