Hardware-based decoding features are also available on scopes based on protocol analysers and help them over-come speed limitations.
“Hardware-based decoding provides a virtual real-time update of the decode trace, and doesn’t degrade the scope’s waveform update rate (which can be up to 1,000,000 waveforms per second). This enhances the scope’s probability of capturing and displaying infrequent serial bus communication errors,” says Bhatia.
In addition to improving the computational throughput of CPUs in software-defined test systems, Moore’s law is driving enhancements in another type of computing device: the field-programmable gate array (FPGA). Essentially, FPGAs are pieces of hardware that you can reconfigure with software. These enable the engineers to reduce test time and perform tests not previously possible without custom hardware.
Satish Mohanram, technical marketing manager, National Instruments India, explains the benefits of FPGA-based encode and decode: “Instead of using software to encode signal information into a protocol-level signal (and vice versa), FPGAs can encode and decode data directly in hardware. This simplifies test system software because it needs to work with only data information, and it makes protocol-level communication possible where predefined test vectors alone are not suitable (for example, when quick decisions are needed based on protocol data). It might also be necessary to quickly transition from receiving to transmitting data on the same line. The test hardware must be able to detect and respond to this case.”
In a nutshell
Enhancing the productivity and the accuracy are important goals for any design house. Protocol analysers are well positioned to help you achieve these goals.
