The RapidSmith Project from Brigham Young University, USA, is a Java package that contains the tools and application program interfaces (APIs) for providing a unique platform to work out experimental ideas and algorithms on modern Xilinx field-programmable gate arrays (FPGAs). The CAD tool allows users to import XDL/NCD, manipulate, place, route and export designs among a variety of design transformations.
As a CAD tool based on Xilinx Design Language (XDL), RapidSmith provides a human-readable file format equivalent to Xilinx proprietary Netlist Circuit Description (NCD). Through xdl executable, RapidSmith can be used to modify designs at any point in ISE’s design flow or even create one from scratch. Packages present in RapidSmith allow parsing and exporting of bitstreams at packet level, and representating frames and configuration blocks in the provided data structures.
The motivation behind Rapidsmith CAD Tool
Project administrators, Christopher Lavin and team, have described the motivation behind the development of RapidSmith in their document titled ‘Rapid Prototyping Tools for FPGA Designs: RapidSmith.’ They felt that the compilation time associated with the FPGA design was very high in comparison with what is required for software systems. A faster compilation process for FPGAs ensures improved productivity for designers as more designs and debugging could be completed within the stipulated time.
Moreover, devices get bigger and bigger with every generation, thereby resulting in no significant improvement in FPGA implementation times.
Although, the target hardware is often available for design-verification during much of the development process, it often goes unused as there is no fast method for its proper utilisation for verification during the design process. Therefore RapidSmith has been developed as a rapid mapping mechanism for design onto an existing FPGA platform to perform rapid design and debug cycles. This, in turn, provides a more interactive development environment for FPGAs.
Challenges in a module based FPGA design flow
There are mainly two challenges faced in the creation of a module based FPGA design flow. First, creation of modules should be fast and simple. The so-created modules should contain as much relative placement and routing information as possible to provide reasonable speedup.
The second challenge is the absence of a framework for commercial FPGAs, which allows the design flow to be built upon. Performing experiments on actual FPGAs ensures a credible speedup and fast build times. “RapidSmith follows a new hard macro based design flow that, like software, would create and use pre-compiled modules (or hard macros) from a library that could be rapidly assembled, placed and routed for a rapid implementation,” describe the project administrators in their demonstration paper. The CAD tool, thereby, overcomes the above-listed challenges and offers an open source framework that makes such a design flow possible on Xilinx FPGA.
Targeting academicians in FPGA CAD research
The CAD tool is targeted at academicians involved in the research of FPGA computer-aided design (CAD). A basic understanding of programming in Java is a prerequisite for using this tool.
Again, users need to have basic knowledge about Xilinx FPGA and XDL, but the detailed documentation of the CAD tool available online will help them be at par with the required knowledge level. The CAD tool is intended for the purpose of research only and should not be used with commercial designs.
What RapidSmith offers
Having discussed the motivation behind and targeted users, let us now have a quick look at the various tools bundled in the software.
Design-analysis tools. If a design is given in XDL format, RapidSmith provides an easy-to-use platform for creating design-analysis tools. A design analyser that tabulates detailed resource utilisation statistics and design properties could also be created.
Design-creation tools. RapidSmith could be used to read and write XDL files. Apart from this, the software allows users to create a circuitry in XDL file format. APIs that create primitive instances customise these instances and even create logical connections between primitive instance pins contained in the tool.
Physical design tools. Creation of physical design tools is very easy with the help of
RapidSmith framework. An interactive hard macro placement tool can be built using RapidSmith.
The use of Java
One of the main priorities behind the development of RapidSmith software is its ease of use. With user-friendly features like an easy-to-use API and automated garbage collection, Java was chosen as the programming language for RapidSmith. The time needed for debug is greatly reduced and the researcher can focus on more fruitful research. The design and device packages in Java alleviate the challenges of using XDL and establish an API to interface with the ISE tool flow through XDL interface.
But many engineers feel that the use of Java as a prototyping platform for FPGA CAD tools is a wrong choice. This is due to its reputation of being a memory hog and slow. But developers of RapidSmith are optimistic in this regard and feel that both speed and memory can be controlled to the point where this is not an issue.
Improving productivity of FPGA designs
RapidSmith is an XDL based rapid prototyping platform for research ideas and algorithms relating to low-level FPGA CAD tools. Hopefully, researchers around the globe will make use of the tool for research to develop its capabilities further and to provide new opportunities for research in FPGA CAD tools.
You may also like: click here
Jai Sachith Paul is assistant professor at Department of ECE, SETCEM, Thrissur
