Electronic devices manufactured today are far more complex than were five years ago in terms of processing power, power consumption, memory, area and performance. To keep up with the market demand for higher bandwidth, more memory and lower power consumption in electronic products, electronics design automation (EDA) companies are rolling out valuable features in their range of software tools for designing electronic chips and systems in a faster, better and cost-effective manner.

EDA tools are also moving to a secure cloud environment, which could lower capital and operation expenditure. More on that and other interesting developments in EDA tools in the following sections.

Fig. 1: Interface of SystemVue 2015.01 showcasing its latest improvements and additions (Image courtesy:
Fig. 1: Interface of SystemVue 2015.01 showcasing its latest improvements and additions (Image courtesy:
Fig. 2: Simulink features new graphical controls and displays for tuning the simulations (Image courtesy:
Fig. 2: Simulink features new graphical controls and displays for tuning the simulations (Image courtesy:

Tools for system-level design
With the proliferation of the Internet of Things (IoT), an open, connected and scalable software tool can be used by developers to accelerate system-level design and verification. Many EDA companies provide comprehensive tools that provide high throughput and quick debugging and compilation. They are also adding new features to boost ease of use and adaptability of the software.

New features in some of the tools for system-level design and verification have been highlighted below. These allow engineers to execute design optimisations swiftly and effectively.

SystemVue. System architects, designers and verifiers mostly use electronic system-level design (ESL) tools to innovate the physical layer (PHY) of next-generation communication systems. It is important to have the right tool to design and validate the PHY layer of communication systems that simplifies this challenging task.

Usually ESL tools iterate the baseband and radio frequency (RF) designs separately in a system. Keysight’s SystemVue validates the entire system at an early stage and then co-verifies it at each step in the process. Common test benches are reused throughout the model based design flow, which reduces design time and verification effort.

The latest release, SystemVue 2015.01, includes a module from MathWorks, MATLAB Script, which replaces mathlang equation parser in earlier versions. Equipped with locally-licensed copies of MATLAB, this module executes MATLAB models from within SystemVue. With updates to almost all libraries and add-ons, a new 5G library has also been incorporated. Instrument support and simulation have been expanded for wide bandwidth systems, especially for radar, 5G and satellite.

Another key feature included is a field programmable gate array (FPGA) programming interface for the M9703A real-time digitiser.

IDesignSpec. Modern systems on chips (SoCs) are quite complex and include a lot of functionality. Specifically speaking, Rinku Singh, design engineer, Agnisys says, “Register and memory-map definitions are becoming tedious, consuming significant implementation and verification time.” Agnisys’ IDesignSpec helps designers to capture register specification and generate the desired code.

Engineers manually read the specification and code RTL or C header files, which is highly undesirable as it is tedious, mundane and costly in terms of both time and resources. In the latest version, IDesignSpec automates this process of generating code from a single specification. The specification itself may be split over a number of individual documents or files.


“Agnisys recently launched Automatic Register Verification (ARV) module, where two separate tools (IDesignSpec and IVerifySpec) are available in an integrated form,” notes Singh. He adds, “IDesignSpec generates Universal Verification Methodology (UVM) environment and custom sequences, whereas IVerifySpec generates the verification plan, imports the existing plan, simulation vendor specific plans and annotated simulation results on to the plan.”

There are some features that were earlier optional for users to use, but in the latest version these work as default. Singh informs, “Tool Command Language Application Programmer’s Interface (TCL API) was optional in an earlier version, but it is now included by default. It helps users create their own outputs from the specification.” He adds, “The latest version completely supports several industry-standard buses like Advanced eXtensible Interface (AXI), Advanced High-performance Bus (AHB), AHB3Lite, Open Core Protocol (OCP), Avalon and Wishbone. This ensures that users can create SoCs with ease.”

ADS. The newest release of Advanced Design System (ADS) 2015.01 includes various improvements over the earlier version. This tool from Keysight Technologies typically covers the complete design flow of a product to manufacturing and is suitable for board, module and system designers.

Silicon radio frequency integrated circuit (RFIC) interoperability with Virtuoso enhancements provides designers with a schematic interoperable process design kit (PDK) as well as pcell support.



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