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Location: Hyderabad
Company: Cadence
About the Role
Experience in model validation with schematics. Strong expertise in modelling especially real number modelling using Verilog-AMS/SV. Some expertise in performance simulation(JTOL) is an added plus. Experience in creating/contributing towards AMS verification plan. Good understanding of analog / mixed signal circuits. Experience in Analog and Mixed signal Verification, understand the usage of tools. Hands on experience in SV, UVM based Verification. Some exposure to functional verification in debugging AMS modelling issues with design and verification engineer. Should be process oriented and have exposure to basic scripting/automation. Good soft skills and experience of working collaboratively in cross site environment.
Responsibilities
- Experience in model validation with schematics.
- Strong expertise in modelling especially real number modelling using Verilog-AMS/SV.
- Some expertise in performance simulation(JTOL) is an added plus.
- Experience in creating/contributing towards AMS verification plan.
- Good understanding of analog / mixed signal circuits.
- Experience in Analog and Mixed signal Verification, understand the usage of tools.
- Hands on experience in SV, UVM based Verification.
- Some exposure to functional verification in debugging AMS modelling issues with design and verification engineer.
- Should be process oriented and have exposure to basic scripting/automation.
- Good soft skills and experience of working collaboratively in cross site environment.
Qualifications
Experience: 4-16 years
Required Skills
Experience in model validation with schematics, Strong expertise in modelling especially real number modelling using Verilog-AMS/SV, Good understanding of analog / mixed signal circuits, Hands on experience in SV, UVM based Verification, Good soft skills and experience of working collaboratively in cross site environment.
Preferred Skills
Some expertise in performance simulation(JTOL), Experience in creating/contributing towards AMS verification plan, Some exposure to functional verification in debugging AMS modelling issues with design and verification engineer, Should be process oriented and have exposure to basic scripting/automation.
