JOB: Design for test Engineer – DFT At DeFT Semiconductors In Bengaluru

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Qualifications and Experience Details

We’re hiring Design for Testability (DFT) Engineers with 4+ years of experience for our Bangalore location.

Key Responsibilities

1. DFT implementation and verification
2. Expertise in using implementation tools like Mentor Tessent Fastscan, Testkompress, Synopsys DFT Compiler, and Tetramax.
3. Strong knowledge in ATPG/Scan, coverage analysis, and EDT compression
4. Memory BIST implementation and verification.
5. Proficient in debugging simulation failures at RTL-level and gate-level
6. Experience with static timing in DFT modes, including constraint issue debugging and timing report analysis.

Location: Bangalore

Experience Level: 4+ years

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Last Date to Apply: December 2024

Email ID for Applicants for sharing the resumes/CVs: [email protected]