Sunday, December 22, 2024

FPGA is an Evergreen, Niche, Not-Easy-To-Get-A-Job Industry

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Good problem-solving skills enable an FPGA engineer to analyse different solutions to a given problem and zero in on designing the solution. A good debugging skill makes one quickly find the design bugs and allows a designer to fix it. He adds, “Though this skill comes only with experience, a strong analytical ability helps an engineer to build expertise quickly.”

Talking about experienced graduates, Kapat says, “For experienced graduates already working in this field, we strongly rely on their digital design fundamentals. If the experience level is of around five years, we expect the engineer to have worked with complete FPGA development cycle. It is expected that the engineer is well acquainted with FPGA development tools from any one of the FPGA vendors—preferably Xilinx/Altera, simulation tools and have hands-on experience with board validation with FPGA-specific debug tools such as ChipScope/SignalTap.”

The engineer should be aware of the FPGA architecture and features of the devices he/she has worked with. She further adds, “But most importantly, we test if the engineer can create a digital circuit for given specifications and requirements.” So, digital design, VHDL/Verilog HDL, synthesis, floor planning and board validations are the skills an experienced engineer must acquire.

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Pay
“FPGA is a growing field for electronic engineers and a majority of the jobs in this specialisation are focussed in the silicon valley of India, namely, Bengaluru. This highly specialised skill is greatly in demand by the IT consulting, engineering and knowledge process outsourcing industries. While starting salaries are not very spectacular—with the correct exposure in this field, a professional with a couple of years of experience can draw seven-figure salaries,” explains Vivek Madhukar, COO, Times Business Solutions.

Talking about eInfochips, Kapat shares that for fresher graduates, the pay package is Rs. 150,000 to Rs. 200,000 per annum whereas for experienced professionals, it varies from Rs. 200,000 to Rs. 1,200,000 per annum depending on their skills.

With respect to Xilinx, “For new college graduates, we recruit from IITs/NITs only at this3A7_Major stage but we will be open to visit other institutions as well as our need will grow. We recruit a very small number of them, and therefore we do not have a need to visit other engineering institutions at this stage from a hiring point of view,” notes Choudhary. “Our compensation packages are competitive and comparable with any other MNC product companies operating in semiconductor and system-level domain,” he further adds.

According to the data provided by TimesJobs.com, 50 per cent of the jobs are for entry-level engineers in the FPGA domain and they are paid anywhere between Rs. 150,000 and Rs. 500,000 depending on their skills and capabilities. Once they gain experience and elevate to junior level, their package lies between Rs. 500,000 and Rs. 1,000,000 approximately. Currently, about 43 per cent of the jobs are for fairly experienced, junior-level professionals. About just 3 per cent and 4 per cent jobs are for mid-level and senior-level experts in the FPGA domain.

Future
FPGA industry is an evergreen industry. The FPGA engineer, especially in a service industry, is expected to work on all aspects of the development cycle. In most of the projects, the RTL design, STA, floor planning and board-level validation needs to be handled by the same FPGA engineer. Based on the project complexity for certain projects, the FPGA engineer handles both the design and verification as well.

Because of many factors including cost and ease of prototyping, more and more designs are getting done in FPGA. Soni says, “You can have smaller design cycle, faster time to market, lower cost for low-volume products, no NRE and many other benefits when doing designs in FPGA.”

“So study well, choose a good project and do it completely, get a good hold over basic concepts and hop onto the niche career in the FPGA industry,” he adds.


The author is a senior technical correspondent at EFY

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