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Location: Chennai
Company: Qualcomm
General Summary
- Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.
- Experience with RTL coding using Verilog/VHDL/System Verilog.
- Experience in micro-architecture & designing cores and ASICs.
- Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc.
- Exposure in scripting (Pearl/Python/TCL).
- Strong debugging capabilities at Synthesis, timing analysis & implementationÂ
- Collaborate closely with cross-function team to research, design and implement performance, constraints and power management strategy for product roadmap.
- Good team player. Need to interact with the other teams/verification engineers proactively.
- Ability to debug and solve issues independently.
Minimum Qualifications
- Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
- 1-3 Years of experience in Synthesis, Constraints and interface timing Challenges. Â Good knowledge of Power is preferable.
