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What you will be doing
As a Physical Designer in this team you will be responsible for full-chip implementation and enabling tape-out of power managed SoC’s using CND toolset. You will also have the opportunity to interact with different global teams towards managing your receivables/deliverables . Furthermore you will be able to take part in challenging fronts in creating and applying new methodologies related to power managed designs
You should have
- Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place and route, CTS, power management/power routing, timing convergence, layout closure with a working experience on Cadence toolset
- Proven hands-on expertise on power management methodologies.
- Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification/chip finishing. Well versed with timing constraints, STA and timing closure.
- Working experience in chip finishing and Tapeout related flows and checks
- Good automation skills in PERL, TCL, tool specific scripting on industry leading Place and Route tools.
- Ability to multi-task and flexibility to work in global environment.
- Good communication skills and strong analytical and Problem solving skills
Basic requirements
- 3-8 years of experience
- Bachelor or Master’s degree
Location: Bengaluru
Company: Texas Instruments
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