Qualification
Bachelor or Master’s degree in Electronics engineering.
3+ years of design experience
Experience with Chip level DFT and Post Silicon debug / analysis
Understanding of DFT architectures like JTAG, Scan Compression Techniques, scan chain insertion and verification.
Must have experience generating scan patterns and coverage statistics for various fault models like stuck at, IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation.
Design experience in MBIST / LBIST is an added advantage.
Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis.
Preferred Skills/Experience
- Experience with TCL /Perl is preferred.
- Effective communication skills to interact with cross-functional teams.
- Join in 15 days
Location: Hyderabad/Noida/Bangalore
Company: Tecquire Solutions Pvt Ltd
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