Normally, false triggering of timer IC 555 takes place during power on, resulting in unwanted output, which starts the timer’s time cycle. The circuit becomes inefficient especially when the load has to be energised only when desired. Here is a simple false triggering eliminator circuit for timer 555.
False Triggering Eliminator Circuit
The circuit is wired in monostable mode and grounded via N/O contact of RL(b) as well as switch S2. When power switch S1 is switched on, the circuit will not be grounded until switch S2 is momentarily pressed. To provide the triggering pulse to the timer at pin 2, press switch S2 momentarily.
To activate the relay for operating the load, switch on the power to the circuit by pressing switch S1 and then S2 momentarily. The resulting output at pin 3 goes high and energises relay RL to operate the load. Now after momentarily pressing S2, the circuit remains on as GND gets connected to N/O contact of RL(b). At the same time, pin 2 is disconnected from N/C contact of RL(b), which prevents further triggering.
The time period of relay energisation (approximately 3 minutes) can be easily changed by changing the values of resistor R1 and capacitor C1 according to the requirement to operate the load. At the end of the cycle, the relay gets de-energised and the circuit becomes ungrounded again.
The article was first published in July 2003 and has recently been updated.