Interactive Analog/Digital Mixed Signal Modeling via Foreign VHDL/Verilog C Interface

By Alessio Brighina, Francesco Giuffrè, STMicroelectronics

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The development of modern electronic modules requires even more appropriate tools to facilitate their early prototyping. Mixed Analog/Digital systems today need simulation platforms based on co-simulation between different analog and digital simulations tools, falling in a higher cost and slower computation times, due to the need of a continuous data transfer among them.

In this article, an analog-digital mixed signal modeling approach based on the conversion of analog Matlab/Simulink model to C code is presented, along with a real case study.

Goal of this approach is to create an interactive simulator, operating-system independent, able to run time-effective Mixed A/D Signal simulations.

The integration of the C code (for analog modules) with the VHDL/Verilog code (for the digital cores) eliminates the need of co-simulation, thus reducing model complexity, cost and improving the code portability.

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In the present work the model of a complete Light Emitting Diodes (LED) driver module is reproduced. Its analog parts were originally modelled in Matlab/Simulink while the Digital core was represented by mean of its related VHDL code. The model of an external Serial Peripheral Interface (SPI) module was also implemented in order to send digital command to the driver and so to simulate the control performed by a virtual Microcontroller.

All this has been achieved realizing an ‘interactive’ user-friendly web Graphic User Interface (GUI), thus enabling to change several system parameters and to modify the devices setting while a simulation is running. Definitively, the tool works just like a ‘live datasheet’ allowing to analyze the device model in dynamic conditions, along with variation of inputs and digital command sent by the virtual Microcontroller. It can be massively used for customers support, marketing activities, load compatibility definition and design support. In the specific case, the final generated Digital Code was built for Modelsim and then successfully tested with NCSim, in order to prove the independence of the approach from the digital simulator.

Introduction

Mixed mode A/D models can be simulated in Matlab or Simulink environments with the support of the EDA Simulator Link that provides a co-simulation interface with commercial HDL simulators from Mentor Graphics, Cadence, and Synopsys. Matlab code or Simulink models can also be used as a test bench for the generation of stimulus for HDL modules provided by designers and for analyzing the simulation’s results. Communication interface may be bidirectional and Matlab/Simulink-HDL modules can be connected in closed loop.

In this way, any mixed A/D model can be virtually simulated, developing models of analog parts and interfacing them with the HDL modules for the digital parts (Fig. 1).

Analog and Digital Subsystems

The advantage of this solution is a high flexibility in the projecting phase. On the other side, full simulation environment, consisting on Matlab/Simulink + Toolbox (at least EDA Simulator Link) and a compatible HDL simulator, must be available for third party users. One way to drastically reduce cost and complexity for using the above tools is to compile analog Simulink parts and integrate them in HDL simulator.

For a given A/D system, the proposed modeling workflow is the following:

  • Build the behavioral Simulink models of each analog model (granularity is up to the purposes)
  • Integrate in the Simulink environment the Digital part (Native VHDL/Verilog) by means of EDA Simulator Link (Co-simulation Simulink/HDL Simulator).
  • Generate standalone C code via Simulink coder for the analog subsystem only.
  • Modify generated code to integrate it with VHDL or Verilog foreign C interface (so obtaining a separate library)
  • Write HDL wrappers for the C analog generated library and top module.
  • The final model requires only a HDL simulator to run (e.g. Modelsim or NCSim).

Foreign VHDL/Verilog C Interfaces

Modern HDL simulators can integrate foreign language codes (e.g. C/C++) for behavioral modules descriptions via external interfaces. Moreover it is possible to implement C subroutines inside VHDL architectures and integrate them with Verilog modules or vice versa.

VHDL C interface is commonly referred as Foreign Language Interface (FLI) or VHDL Procedural interface (VHPI); FLI and VHPI implementations depend by HDL simulators and are usually described in their own reference manuals. On the contrary, Verilog Programming Language Interface (PLI) is a standard procedural interface and is described by IEEE 1364-2005 Language Reference Manual and many third part ones.

From Simulink to C Code Conversion

Simulink Coder (formerly Real-Time Workshop) is an application of Mathworks which generates and executes C and C++ code from Simulink diagrams, Stateflow charts, and MATLAB functions.

It automatically builds modules that execute in Real-Time or Stand-alone non-real-time simulation for most Simulink blocks and many MathWorks products (Fig. 2).

working flow

The generated source code matches the functionality behavior of original MATLAB/Simulink one with high degree of fidelity.

Selecting ‘Generic Real-Time target’ (grt) option in ‘Code Generation’ pane, once the code generation is complete, several C/C++ files are generated in the ‘X_grt_rtw’ directory (where ‘X’ is the model name). Number and size of generated files depend on the model complexity.

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2 COMMENTS

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