Cadence introduces its machine learning based tool that aims to increase productivity in chip design industries.
Chip designing is a very complex problem and involves a lot of simulations and verifications apart from designing. However, some aspects of chip designing can be predicted, and by automating those design aspects, high productivity can be achieved. Cadence announced its Cerebrus Intelligent Chip Explorer RTL-to-signoff flow that offers chip designers, CAD teams and IP developers, the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA).
The tool has a reusable and transportable reinforced learning model that increases effectiveness with each use. Moreover, this tool is cloud enabled on Amazon Web Services (AWS) and other leading cloud platforms to provide more efficient on-site and cloud compute resource management capabilities.
The ML based tool quickly finds out the design flow solutions, reducing the time to get better results. It allows a single engineer to optimize the complete RTL-to-GDS flow automatically for many blocks concurrently, allowing full design teams to be more productive. Plus, it has a powerful user cockpit, allowing interactive results analytics and run management to gain valuable insights into design metrics.
More information can be found at cadence.com.
