MosChip Technologies the pioneer of the fabless semiconductors in India has recently released an enhanced simplex High-Speed Serial Trace Probe (HSSTP) PHY macro. It has a link-layer supporting data transfer capabilities of up to 12.5Gbps per lane in 6nm FinFET technology. The HSSTP PHY and Link Layer enable Real-Time monitoring of on-chip signals/bus, High-Speed Debug/Test data transfer, and Silicon Debug for advanced FinFET SoCs with high-performance Arm® CPU cores.
Headquartered in Hyderabad, the company has developed many connectivity-based products over the years. They provide turn-key digital and mixed-signal ASICs, design services, SerDes IP, and embedded system design solutions. To meet the growing needs for higher bandwidth trace with fewer SoC pins, MosChip has added the multilane HSSTP to its transceiver portfolio. According to the company, even the Arm®CoreSight ecosystem uses MosChip’s HSSTP link layer as one of the components of the standard Serial Trace Port (STP). The Trace Port Interface Unit (TPIU) sends data through an STP that can use a serial high-speed interface (SERDES). TPIU interface complies with the Arm® CoreSight protocol and the Link layer complies with the Aurora 8b/10b Simplex specification.
“MosChip’s HSSTP IP can be paired with any HSSTP compatible receiver system to create a flexible debugging platform customizable for nearly every silicon bring-up strategy,” said Swamy Irrinki, VP of Marketing and Business Development at MosChip.
To enable the capture of multiple lanes of high-speed serial trace, Arm® has created the HSSTP trace probe which is ideal for situations where it’s necessary to collect a large amount of trace data and/or where SoC termination count rules out parallel trace
“This is a major milestone for MosChip, which highlights our strategic focus to develop niche SerDes PHY IP as per customer requirements,” said Venkata Simhadri, MD/ CEO of MosChip.
