At Intel Innovation event in Silicon Valley, Intel announced the Intel Agilex D-series FPGA and SoCs, which are ideal for midrange FPGA applications which require highest performance, low power and smaller form factors such as, studio camera and 8K video transport, and wireless infrastructure (macrocells, front and back haul, and radio units).
The tremendous market acceptance of the original Intel Agilex FPGA and SoC families combined with Intel’s relentless pursuit of innovation resulted in the Intel Agilex FPGA family enhancing the Intel Agilex architecture with new features and different characteristics to suit an even wider range of applications. These new capabilities are increasingly important to support the need for parallel concurrent workloads. The emerging trends for most midrange applications demand lower power consumption and higher performance . While the need for more performance keeps accelerating, this is where the Intel’s process technology delivers.
This new family of Intel FPGA and SOCs incorporate many new features such as an upgraded hard processor system (HPS), Enhanced DSP with AI Tensor Block, MIPI I/O support, and hardened time-sensitive network controller (TSN). Intel Agilex D-Series devices also share significant features with other Intel Agilex FPGA and SoC families including the 2nd-generation Intel® Hyperflex™ FPGA Architecture and high-speed SerDes transceivers. Combined, these features make Intel Agilex D-Series FPGAs ideal for a wide range of midrange FPGA applications.
Intel has taken advantage of semiconductor process advances to create the Intel Agilex D-Series FPGAs, which extends the Intel Agilex FPGA portfolio to lower logic densities. Where earlier members of the Intel Agilex FPGA and SoC families are manufactured with the Intel 10 process node, the Intel Agilex D-Series devices are manufactured using Intel 7 technology, which is now a mature process that Intel uses to manufacture high-volume CPUs including the 12th generation Intel® Core™ CPUs and 4th Generation Intel® Xeon® Scalable server CPUs. The new Intel Agilex D-Series FPGAs and SoCs combine the advanced Intel 7 technology with 2nd generation Hyperflex FPGA Architecture to deliver 2x better fabric performance per watt versus competitive 7nm FPGAs1.
The Intel 7 technology permits Intel to create programmable-logic devices that integrate fast I/O circuits including high-speed, 28 Gbps SerDes transceivers and flexible general-purpose I/O banks along with programmable logic and hardened IP blocks, all on one monolithic silicon die. Using a thick gate-oxide transistor variation of the Intel 7 technology allows the Intel Agilex D-Series FPGAs to have both high-speed I/O banks and high-voltage I/O banks that can support 3.3 V operation, as shown in the following graphic:
In addition, Intel Agilex D-Series FPGAs and SoCs incorporate several hard IP blocks that are new to the Intel Agilex FPGA family including the Enhanced DSP with AI Tensor Block, a time-sensitive networking (TSN) block, a MIPI interface, and an upgraded hard processor system (HPS) that includes a dual-core Arm Cortex-A76 processor and a dual-core Arm Cortex-A55 processor. Arm DynamIQ technology allows software developers to harness the Arm Cortex-A76 and Arm Cortex-A55 CPUs into a single integrated cluster that delivers improved power and performance for a wide variety of applications.
The Enhanced Digital Signal Processing (DSP) with AI Tensor Block within the FPGA fabric of these new Intel Agilex FPGAs and SoCs inherit the design of the variable-precision DSP blocks in the earlier Intel Agilex device families, which already offer AI capabilities. In addition, it adds features derived from the tensor block used in the Intel® Stratix® 10 NX FPGAs. The Enhanced DSP with AI Tensor Block introduces two new important operations: the tensor processing capability for AI and complex number support for signal processing applications such as FFTs and complex FIR filters.
The first mode enhances AI with the INT8 tensor mode, which provides twenty INT8 multiplications within one Enhanced DSP with AI Tensor Block, and increases INT8 compute density by 5x versus earlier Intel Agilex device families. The tensor mode uses a two-column tensor structure with both INT32 and FP32 cascade and accumulation capability, and also supports a block floating exponent for improved inference accuracy and low-precision training. In addition, the AI capability of the variable precision DSP functionality has also been enhanced. The vector mode has been upgraded from four INT9 multipliers to six INT9 multipliers. These modes are extremely useful for AI-centric tensor math and for various DSP applications.
The second new mode, the complex-number operation, doubles the performances of the tensor block when performing complex-number multiplication. Previously, two DSP blocks were needed for complex-number multiplication, but this new family of Intel Agilex FPGAs and SoCs can multiply 16-bit, fixed-point, complex numbers within one Enhanced DSP with AI Tensor Block.
Intel’s software tools will enable ease of use to optimize the power and area footprint of AI resources. This is the FPGA industry’s only single push-button-flow, incorporating AI frameworks (such as TensorFlow and PyTorch) for specific throughput and latency targets and creating custom-sized inference IP.
These new hardware features plus the high-performance, low-power FPGA fabric make Intel Agilex D-Series FPGAs and SoCs ideal for use in midrange FPGA applications across many markets from the network’s edge to its core including wireless and wireline communications, video and audio broadcast equipment, industrial applications, test and measurement products, medical electronics, and military/aerospace applications.
