STMicroelectronics today announced the launch of the Intelligent Sensor Processing Unit (ISPU) that combines a Digital Signal Processor (DSP) suited to run AI algorithms and MEMS sensor on the same silicon.
In addition to reducing size over system-in-package devices and cutting power by up to 80%, merging sensor and AI puts electronic decision-making in the application Edge. Here, it facilitates the Onlife Era where innovative products enabled by smart sensors are able to sense, process, and take actions, bringing the fusion of technology and the physical world.
The Onlife Era acknowledges living with continuous assistance from connected technologies, enjoying natural, transparent interactions, and seamless transitions, with no discernible distinction between online and offline. With the ISPU, ST is enabling this era by helping to migrate intelligent processing into sensors that support the fabric of life: no longer at the Edge but in the Edge.
ST’s ISPU provides substantial benefits in the four Ps: power consumption, packaging, performance, and price. The proprietary ultra-low-power DSP can be programmed in C, familiar to many engineers. It also allows quantized AI sensors to support full- to single-bit-precision neural networks. This ensures superior accuracy and efficiency in tasks such as activity recognition and anomaly detection by analyzing inertial data.
“While technically challenging, integrating ST’s sensors on the same piece of silicon with our ISPU does improve sensor-based systems from an online experience to an Onlife one. It advances the sensor’s features to speed decision-making by reducing data transfers, enhancing privacy by keeping data local, while reducing size and power consumption, which cuts costs,” said Andrea Onetti, Executive Vice President, MEMS Sub-Group, STMicroelectronics. “Moreover, the ISPU is easily programmable with commercial AI models and can ultimately operate with all of the leading AI tools.”
Technical Notes for Editors:
ST’s proprietary, C-language-programmable DSP is an enhanced 32-bit Reduced Instruction Set Computing (RISC) machine. It is extensible (in the chip-design phase) for dedicated instructions and hardware components. The processor offers a full-precision floating-point unit, uses a fast four-stage pipeline, operates from 16-bit variable-length instructions, and includes a single-cycle 16-bit multiplier. Interrupt response is a spritely four cycles. ST’s sensors with ISPUs will be packaged in standard 3mm x 2.5mm x 0.83mm packages and will be pin compatible with their (ST) predecessors, allowing quick upgrades.
Combining the sensor and ISPU is also a big power saver; ST’s calculations show a 5-6x saving over System-in-Package approaches in sensor-fusion applications. They also show a 2-3x saving in RUN mode.
