The chip is algorithm and host processor agnostic and can be integrated into existing environments without redesigning the entire system
VSORA, a provider of high-performance silicon intellectual property (IP) solutions for artificial intelligence (AI), digital communications and advanced driver-assistance systems (ADAS) applications, has unveiled a family of PetaFLOPS computational companion chips to accelerate Level 3 (L3) through Level 5 (L5) autonomous vehicle designs.
Tyr, a family of three different chips called Tyr1, Tyr2 and Tyr3, uses a fully programmable and scalable architecture that tightly couples digital signal processing (DSP) cores with machine learning (ML) accelerators necessary to design L3 through L5 autonomous driving vehicles.
Delivering between 258-trillion and 1,032-trillion operations per second and consuming as little as 10 Watts, Tyr allows users to implement autonomous driving functions previously not commercially viable. The Tyr companion chip is algorithm and host processor agnostic and can be integrated into new or existing environments without the need to redesign the entire system.
“We are proud to be the first to offer the ability to rapidly move to full autonomy utilising what designers have already invested in,” remarks Khaled Maalej, CEO and founder of VSORA.
The modular architecture of the Tyr family can meet the challenges of autonomous driving. With 1,032 TeraFLOPS of computational power, the Tyr3 processes an eight-million cell particle filter using 16-million particles in less than 5 milliseconds (msec). A full-high-definition (FHD) image with Yolo-v3 takes less than 1.6 msec leading to a throughput of 625 images per second.
The Tyr family achieves more than 80% usage efficiency and eliminates the need for expensive hardware accelerator or special cooling solutions.
