Incubated at IIT Madras, the fabless semiconductor startup, Mindgrove Technologies, has developed a microcontroller chip operating on a 28-nanometre technology node with a SHAKTI core, at a speed of 700MHz for IoT applications, signal processing, machine learning, and characterisation in signal processing and vision domains. The chip leverages built-in security features and enhanced performance for tasks like fingerprint scanning and high-speed motor control, facilitating feedback and control on a single chip. In an exclusive chat with EFY’s Yashasvini Razdan, co-founders Shashwath T.R. and Sharan Srinivas J. dished out interesting details about technology nodes in chip design
Q. Why did you choose to work with a 28-nanometre technology node?
A. Sharan: Internally, we refer to the 28-nanometre process node as the ‘Goldilocks node’ because it offers sufficient speed, incorporates power-saving features in the node’s design, and is relatively cost-effective. It is the last process node where traditional planar transistors are used before transitioning to FinFET transistors, which are more complex and expensive, particularly in the case of 16-nanometre and lower nodes. Developing for FinFET nodes presents greater challenges and costs, making 28 nanometres an ideal choice that provides the desired performance, power efficiency, and manageability of process technology without breaking the bank. Hence, the fitting nickname ‘Goldilocks.’
Shashwath: Though it was not a primary factor in our decision-making, the 28-nanometre process node does not pose export control issues from the US. Access to this node is freely granted. In contrast, for the latest process nodes, a separate licence is required, and the associated paperwork could have caused significant delays, possibly extending to around six months or even longer. So, beyond its technical advantages, the 28-nanometre node also offers streamlined access, aligning perfectly with our needs for the first year of development.
Q. Can you give me an example of where 28-nanometre nodes are used in real life?
A. Sharan: Xilinx FPGAs, such as Artix 100 and DS 200, are typically fabricated at 28 nanometres. The first-generation Vertex 7 series was produced at 28 nanometres. The very first version of the Apple Watch was manufactured using a 28-nanometre process. Many automotive chips are manufactured using the 28-nanometre process.
Q. How does one choose a process node for a particular chip?
A. Sharan: The choice of process node varies depending on the application and use case. It also depends on when that chip was initially designed. Several smartphone chips from around 4 to 6 years ago commonly used the 28-nanometre node. Until about two years ago, most entry-level smartphones, falling within the price range of 6000 to 15,000 rupees, commonly used chips based on the 28-nanometre node. These smartphones typically feature processors from MediaTek. However, in 2020 and 2021, there was a shift towards the 16-nanometre process, which has become the standard even for lower-end smartphones. This transition marks a notable evolution from this category’s previously widespread use of the 28-nanometre process.
Q. What is the reason for using higher technology nodes in the automotive sector?
A. Shashwath: In the automotive sector, this choice is driven by considerations related to thermal management. In contrast to FinFET transistors, where the fins are closely packed and radiate heat outward, 28-nanometre chips have a different configuration that allows them to dissipate heat more effectively. The orientation of the fins plays a crucial role in how heat is managed. FinFETs, with their vertical fin design, tend to radiate heat upwards, potentially affecting adjacent components. Thermal dissipation can indeed be a challenge in the automotive industry. The ambient temperature in which these chips operate is already relatively high. As a result, many controller-class chips inside electronic control units (ECUs) in automobiles are manufactured using the 28-nanometre process or higher.
Q. Why are smaller technology nodes garnering so much attention?
A. Sharan: In the realm of smartphones, only so much physical space is available. Yet, as consumers, we demand vast features within these compact devices. We want to stream Netflix in 4K, play games seamlessly without lag, and achieve a gaming experience akin to what we get on a PC with a dedicated Nvidia GPU, all within this limited real estate. The challenge becomes squeezing as much computational power as possible into a small area, hence the competitive push towards chips like the 10, 7, 5, 4, nanometres, or other variants that aim to maximise performance within constrained dimensions.
Q. How do smaller technology nodes impact the design of different categories of electronic devices?
A. Shashwath: As transistors shrink, their power consumption decreases. This power efficiency is vital in devices like smartphones, where extended battery life is a top priority. However, in certain contexts, such as electric vehicles (EVs), where the power consumption ranges from a few watts to several kilowatts due to the motor’s requirements, the impact of shaving off a few dozen watts is relatively insignificant. Therefore, design practices may differ for these diverse use cases, and what’s essential for a smartphone may not apply to an EV.
The second area where scaling down is significant is in servers for data centres and cloud computing. Despite the seemingly ample space, data centres face heat dissipation and spatial optimisation challenges. The proximity of racks can lead to heat transfer, making efficient cooling crucial, especially when attempting to maximise data centre efficiency.
Q. Do the same rules apply to industrial and automotive sectors as well?
A. Shashwath: Our thesis underscores the notion that data centres and mobile devices have long dominated the tech landscape, inadvertently neglecting critical features in other sectors like industrial and automotive. These relatively neglected aspects include functional safety and security, paramount in industries beyond the relentless pursuit of speed and power. The potential for significant financial gains in these sectors also drives the pursuit of speed. When the risk-to-reward ratio is favourable, prioritising those areas makes sense. Over the past 15 years, the focus has been on optimising for smartphones, but the landscape is evolving. There is no longer a need for universal smartphone optimisation. Instead, the emphasis should be on feature optimisation and tailoring power, performance, and area considerations to the specific use case. As long as it meets the requirements of the given application, it is deemed sufficient.
Q. What are the factors to consider while designing a chip for the automotive sector?
A. Sharan: Automotive regulations and design requirements are among the most stringent, only exceeded by those in military and space applications. While the military domain often operates at lower volumes, which sets it apart, the automotive industry requires top-tier quality and compliance at a significant scale. Automotive companies typically commit to a chip or a specific hardware configuration for a decade or more. They require long-term support, extensive testing, and other assurances. Our first chip is not intended to be automotive-certified. However, automotive certification is a significant consideration in our approach to design. We aim to align ourselves with this high-quality standard, although achieving it at scale may take time. While 60% of automotive quality falls short of full automotive-grade certification, it represents a high level of quality, especially for microcontroller-class chips. Offering this level of quality within the microcontroller price range means that a chip can withstand heat and humidity, maintain speed, and remain stable, making it a robust and dependable choice for various use cases involving microcontrollers.
Q. What are the factors to keep in mind to maintain power efficiency and a low-power design?
A. Sharan: Efficiency can be prioritised by avoiding unnecessary components and features in the chip design. At Mindgrove, we opt for the 28-nanometre process for microcontrollers rather than the 65-nanometre or 45-nanometre options that are commonly used. This unconventional choice challenges us to create a well-designed chip capable of delivering the required performance without resorting to excessive complexity or gate counts, resulting in power efficiency. Our primary emphasis is on optimising performance, and then we progressively eliminate components and features until we achieve the desired power consumption. We aim to create a chip perfectly suited for its intended purpose, effectively a ‘right-sized’ chip for the task at hand.
Q. How would domestic semiconductor manufacturing impact chip design and development?
A. Shashwath: If a foundry capable of meeting our requirements were to emerge in India, it would be highly appealing. This could significantly reduce costs and offer advantages in terms of both time and the logistics supply chain compared to dealing with overseas foundries. International dealings can be cumbersome. It is important to minimise lead times in the supply chain to ensure swift product delivery, especially when dealing with large-scale operations involving millions of shipments annually. This can lead to substantial cost savings that significantly affect the bottom line. Another intriguing prospect is if someone sets up ATMP (assembly, test, and packaging) facilities in India. We do have such facilities but they are just focusing on entry-level capabilities, which are relatively less challenging to set up.
Sharan: Starting ATMP facilities with QFN or QFP packaging can be a significant step. These package types already have a substantial market in India. However, it becomes even more compelling when it comes to BGA (ball grid array) packaging. This aligns with the considerations of power, performance, and area calculations. BGA packages are particularly advantageous when transmitting data rapidly and efficiently.
