A wealth of opportunities for semiconductor manufacture ing are becoming available in the ‘more than Moore’ 2.5D/3D world. Yole Développment of France expects the shipment volume of 3D IC wafers to reach 10 million units in 2012. The semiconductor ecosystem, comprising design-houses, fabs and foundries, assembly and test providers, EDA developers and research institutes, needs to go through a learning curve as it is now necessary to have an ecosystem optimised for converting such technologies into high-volume manufacturing.
At the SEMICON Singapore 2012 event, Dr Ho-Ming Tong, GM and chief R&D officer of the Advanced Semiconductor Engineering Inc. (ASE) Group, the world’s largest provider of independent semiconductor manufacturing services in assembly and test, commented: “Despite progress in 3D-IC development over the years, challenges remain in the areas of cost control, design, mass production and testing in the lead-up to commercialisation. Given the readiness of silicon interposer-based 2.5D-IC technology to move to the next stage, its deployment will expedite migration from the 40nm node to 28nm. With computing and smart devices fuelling the growth of the market, commercialisation of 2.5D and 3D ICs may take place in 2013.”
To address the challenges of taking 2.5D/3D systems to high-volume manufacturing, collaborative partnerships are very critical.
“IME has established strategic partnerships with leading players in the semiconductor ecosystem to co-develop cost-effective 3D-IC integration and process technologies in Singapore. Our new 300mm advanced packaging facility will provide deeper and broader capabilities to our partners to overcome the challenges in 3D IC,” informed Prof. Dim-Lee Kwong, executive director of the Institute of Microelectronics (IME)—a research institute of the Science and Engineering Research Council (SERC), Agency for Science, Technology and Research (A*STAR).
James Amano, director, International Standards, SEMI, USA, announced during SEMICON West 2012 that the SEMI 3DS-IC Committee, formed in late 2010, had approved its first standard for publication. Pending successful procedural review, the document will be published as “SEMI 3D1, Terminology for Through-Silicon Via (TSV) Geometrical Metrology.”
SEMI 3D1 will provide a starting point for standardisation of geometrical metrology for selected dimensions of TSVs. The Inspection & Metrology Task Force recognised the need for such a standard because although different technologies can measure various geometrical parameters of an individual TSV or an array of TSVs—such as the pitch, top diameter, top area, depth, taper (or sidewall angle), bottom area and bottom diameter—it is currently difficult to compare results from the various measurement technologies as parameters are often described by similar names but actually represent different aspects of the TSV geometry. SEMI 3D1 is an important first step in promoting common understanding and precise communication between stakeholders in the 3D-IC manufacturing supply chain.
Challenges with 2.5D/3D technology
The challenges in moving to 2.5D/3D technology relate to design, fabrication, assembly and testing of 2.5D/3D ICs.
Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems (India), says, “With the accelerating demand for higher bandwidths, low power and mounting density, a lot of IC design teams are trying to adopt 3D-IC technology with TSVs. 3D ICs not only promise improved performance and reduced costs but also assure ‘more than Moore’ integration by packing a great deal of functionality into small form factors. While 3D-IC holds a lot of promise, it is still evolving and has design and verification challenges which need to be addressed.”
3D ICs with TSVs do not need a new 3D design system for digital design, analogue/custom design and IC/package co-design, but they do need some new capabilities. They also require the following for a successful interconnection of 3D-IC dies:
1. As redistribution layers (RDLs) are typically formed on the back of the die, bumps can be placed on both front and back.
2. TSVs can be drilled between the first metal layer and the back-side RDL. These may have a diameter of 1 to 5 microns.
3. Micro-bumps (much smaller flip-chip bumps) have to be aligned to create a data path from one die to another.
Ahuja cites some of the challenges involved:
System-level exploration. System-level exploration for 3D-IC TSV technology is a convergence of silicon and packaging with the design, making it possible to conceive and design new architectures. To fully benefit from 3D-IC TSVs and make this technology cost-effective, different 3D architectures need to be considered and evaluated at a very early stage.
