In the test area, the biggest requirement is providing known-good-die (KGD) to the 2.5D or 3D assembly process in order to ensure a profitable yield. The term ‘KGD’ means more comprehensive testing needs to be used during wafer-level testing. For 3D (stacked die) in particular, the test access infrastructure for routing test data and results to and from any of the dies within the vertical stack is a critical need.
This is a new requirement because all but the bottom dies have connections only to their immediate neighbours and no direct access to package pins. A dedicated access infrastructure must be incorporated within each die of a vertical stack in order to route test data and results up and down the stack. Since the bare die may come from different sources, standardisation of this infrastructure will be needed to ensure proper interoperability between all dies. The IEEE P1838 working group is currently developing such a standard with direct involvement of Mentor.
Sawicki shares: “Multi-die scenarios also create the need for system representations that can accurately represent new elements in a consistent manner, and allow rapid prototyping and optimisation across multiple dies. The EDA solutions for 2.5D (interposed based) are well in hand and do not pose a technology barrier. Full 3D (chip stacking with TSVs) for homogeneous designs (e.g., processors or other logic systems split across multiple dies) is another matter. That will definitely require significant EDA development and some re-architecting of the design tools. These tools are now in development and are expected to be available when the market demand materialises.”
Collaborative effort required
Some kind of collaborative approach is essential to harness 2.5D/3D-IC technologies successfully.
Ahuja explains: “Collaboration and building a well-defined ecosystem are crucial for successful design and usage of 3D ICs. To support 3D IC for EDA tools, there are additional components which need a deeper level of understanding. Optimising system cost with the shortest possible turnaround time is a major challenge which is not possible without an integrated approach to 3D-IC design. Since many 3D stacks combine digital and analogue/RF circuitry, a strong analogue/mixed-signal capability plus a robust IC/package co-design capability and PCB layout system are critical for providing a ‘complete’ 3D-IC realisation methodology.
“3D-IC design should be a shared effort among system architects, package designers, IC designers of various dies, PCB designers and DFT engineers. That calls for a system that can handle the handshake between different platforms, close collaboration between different design environments, and co-design among groups that have historically worked separately. Handoffs between the same company’s designers are difficult enough, and 3D-IC die handoffs could be between different companies or participants in the ecosystem.”
According to Ahuja, while EDA tools can help minimise some of these interactions by providing a common platform, the overall design task gets challenging when dies come from different places and are implemented in different environments. A proper handoff point must be agreed upon by the industry to make it easier for IC designers to exchange design data. Therefore collaboration within the ecosystem becomes crucial.
Standards development activities are going on at the Silicon Integration Initiative (Si2), SEMI and Sematech. The IEEE P1838 Test Working Group is working on 3D-IC DFT architectures. In the memory domain, there is a lot of activity going on at JEDEC, which has ratified the wide input/output (I/O) memory standard. Micron and Samsung have jointly announced formation of the High density Memory Cube (HMC) Consortium, which seeks to develop HMC memory stacks that can be integrated into 3D-IC systems.
“Cadence has invested significantly in ecosystem collaboration for 3D ICs. It has worked with IMEC on DFT architecture, which was later given to the IEEE P1838 working group. Cadence is a working member in Si2 3D TABs on power, thermal and path finding. It is closely involved with GSA 3D-IC working group efforts to bring collaboration in the industry in terms of business models and other topics. Cost-effective, adoptable technological evolution and ecosystem collaboration are essential for bringing 3D ICs with TSVs into the mainstream,” Ahuja shares.
Key issues limiting 3D TSV HVM and need for standardisation
According to Ahuja, one of the biggest questions for any new memory technology is whether there is an industry structure to support it. Industry efforts are underway to standardise wide-I/O DRAMs in the areas of performance, protocol, number of banks and channels, and number and arrangement of TSVs. Such standardisation will create a viable market in which DRAM manufacturers can sell their standard dice to multiple customers. For their part, customers will have multiple compatible devices to choose from. Therefore standardisation is key to the growth of 3D ICs.
